Memories of the Future

At this year's International Electron Devices Meeting (IEDM), to be held Dec. 8-10 in Washington, papers will be presented on all of the main memory types — DRAM, SRAM and flash — as well as alternative memories under development such as magnetic RAM and ferroelectric RAM. Following are some of the highlights:

A record flash cell: Samsung researchers will describe how they built the smallest NAND-type flash memory cell ever (0.025 µm²), for a 4 Gb flash memory chip at 70 nm design rules.

A small, fast flash: Flash memory is dense, but relatively slow. A team of researchers from Renesas/Hitachi will describe how they built the first multi-level AND-type flash cell with high density (2 F²) and programming throughput of 10 MB/sec, at 90 nm design rules.

No errors in memory: SRAM is a fast memory type, meaning data can be written to it and accessed quickly. But it isn't very dense. The 0 and 1 values are represented in its memory cells by the absence or presence of charge in capacitors. As SRAMs scale down, the capacitors become smaller and therefore can't hold as much charge. This increases the possibility of soft errors. To insulate and increase the charge in the capacitors, Samsung researchers for the first time fabricated a metal-insulator-metal (MIM) capacitor on top of the cell's storage node. They used this architecture to build the smallest SRAM cell ever (0.48 µm²), using transistors with 70 nm channels. These cells made possible a high-performance 72 Mb SRAM chip.

Toshiba researchers have fabricated an 8 Mb DRAM with a cell size of 0.11 µm2, and integrated it with three-level copper/low-k interconnects. (Source: Toshiba)

Chalcogenide phase-change memories: Chalcogenide has stable amorphous and crystalline states, and is used in rewriteable CD/DVDs. Researchers are looking at it as a potential low-cost, highly scalable, non-volatile memory. Conceptually, there is an array of cells consisting of top and bottom electrodes (the bit and word lines) with a layer of chalcogenide sandwiched between them. When a current passes through the electrodes, it heats the material, causing it to change state. Stephen Lai of Intel will review the physics, operation and current status of the technology in a paper in the Emerging Technologies session. Issues he will cover include the material's potential to be scaled down to the 22 nm node; efforts to reduce switching current for low-power use; cell design; and whether it can be manufactured in high volumes and at low cost.

A paper from Macronix International researchers also deals with this memory type, in a different session. In their approach, the chalcogenous material is always in the amorphous state. However, it can exist in one of two "threshold" amorphous states that can be read as 0 or 1. No access transistor is needed; the chance a cell can be misread is eliminated; and the theoretically densest architecture (4 F²) is possible, as are fast read/write times and low-voltage operation.

Hybrid silicon/organic molecular memory: Nanoscale size, low-voltage operation, multiple-state properties and low cost would be the likely advantages of memories built from organic molecules instead of silicon. But they're a long way off. A team from North Carolina State University will argue that a hybrid silicon/molecular approach provides a good bridge between conventional CMOS and future molecular-only technologies. They fabricated N+ or P+ pockets embedded in p-well or n-well silicon substrates, and used these sites to move electrons on or off an organic molecule. The result was a memory device that exhibited multiple-state behavior.

Direct tunneling: This is the movement of electrons across a barrier according to quantum mechanics principles. Gain-type memories based on this principle have been described before, where electrons cross a barrier and trigger a second transistor when the channel potential in a control transistor is changed. This happens very fast, at very low voltage, and with good retention times, leading to the possibility these small devices might someday replace both DRAM and flash memories. At IEDM, Samsung researchers will discuss such a memory cell technology, which they say is highly scalable and can be integrated with normal CMOS processes using 240 nm design rules.

For additional information on wafer processing, go to www.semiconductor.net/wafer.