Innovative Packaging Concepts for Ultrathin ICs

The increasing demand on miniaturized and flat packaging technologies is driven by the trend toward small and portable electronic systems. Because of the requirements of modern BGAs, smart cards or chip-size packages, the thickness of ICs has been reduced considerably relative to original wafer thickness. Because of their low height, low topography of assembled chips, and mechanical flexibility, these chips are ideal for integration in thin and bendable systems or vertically stacked systems.

The advantages of thin ICs open a large field of new and interesting applications in microelectronics. However, wafer thinning has its impact on the subsequent assembly process. Dicing, handling, mounting and interconnection processes of thin ICs must fulfill particular requirements, but also offer new and innovative solutions.

Wafer thinning has become a key technology for the semiconductor industry during recent years. Most modern packaging technologies require ICs to be thinner than the original wafer thickness. To reach this goal, convenient processes have been developed, and efficient thinning equipment is available. Today, chip thickness of semiconductor products like smart cards, contactless labels or power devices is below 250 µm, and will be reduced further.

1. Smart label with transponder IC, integrated together with a screen-printed coil on paper.

2. Thinned IC with piezoresistors acting as strain gauge.

Further impulse for wafer thinning comes from the field of microelectromechanical systems (MEMS), where thin silicon has been traditionally used in pressure transducers, accelerometers, etc., as springs or membranes. Mostly, these thinned chip areas are manufactured by bulk micromachining with anisotropic etching. Frontside passivation during the etch process and CMOS compatibility have always been a problem for manufacturing such devices. Wafer thinning delivers a new approach for MEMS fabrication. Figure 2 shows a thinned chip with implanted piezoresistors acting as strain gauge. These chips can be mounted on curved surfaces. Integrating CMOS circuitry together with sensor elements can be easily achieved.

Other innovations arise because silicon wafers can be thinned down to a thickness that can be fully accessed by different wafer processing techniques. An extreme example for the new possibilities of ultrathin silicon is the fabrication of stacked wafers. Figure 3 shows a cross-section of a 10 µm thin wafer bonded to another CMOS wafer together with its planar processed vias.

3. Ultrathin silicon used for vertical IC stacking. Top wafer is thinned to 10 µm, bonded to the bottom wafer and interconnected by interchip vias.

A standard wafer thinning procedure consists of a sequence of grinding, fine grinding and etching, which are well adjusted to each other to deliver the required final thickness, minimum thickness variation and best surface quality. For thin wafer applications, special focus must be given to the damage induced by grinding to the rear side of the wafer, which extends 5-15 µm from the grinded surface into bulk silicon. This distorted layer, which reduces fracture strength considerably, is most often removed by a wet-chemical etching process using isotropic silicon etchant HNO₃/HF/H₃PO₄.

Below a remaining thickness of 100 µm (for 150 mm silicon wafers), more and more difficulties arise with the standard wafer thinning process. Besides troubles with handling equipment, a main problem is the immense increase in the risk of wafer breakage, which means the worst case in semiconductor manufacturing. To manage this, problem-handling substrates are used. The device wafer to be thinned is reversibly mounted to another wafer, which acts as a carrier. Because of this approach, handling problems in standard equipment are avoided, and the risk of breaking a wafer is negligible. Using this technique, silicon wafers can be thinned to a residual thickness of 10 µm. Total thickness variation is in the range of 0.5-2 µm.

Although several detail problems of wafer thinning below 50 µm are still under development, different commercial CMOS wafers (e.g., for smart cards or RFID labels) have been thinned successfully and without substantial loss of yield. Fabrication of ultrathin wafers will soon become a standard procedure. But packaging technology has to proceed with the progress made at wafer level. Assembly of ultrathin chips requires and enables new developments from dicing to final packaging.

The first step moving from ultrathin wafers to ultrathin chips is an adequate dicing process. Normal sawing with a diamond blade can be used, but the sawing damage at the chip edge seriously reduces fracture toughness of the die, an issue that is rather important for integration in flexible systems. Therefore, a process called "dicing by thinning" is a better approach for thin ICs.

This method begins before the thinning procedure. In the first step, trenches are sawn in the scribelines of the wafer with the depth being the final chip thickness. After bonding the device wafer to its handling substrate, thinning is performed until the trenches are opened during the final spin-etching process. In this case, isotropic silicon etchant not only removes grinding damage, but also microcracks and notches induced by the sawing process at the chip edge. This effect is shown in Figure 4 , which compares chip borders for different dicing methods.

4. Comparison of chip borders for different methods of dicing thin wafers (shown is thinned side).

Also shown in this figure is the result of using dry etching instead of mechanically sawing for prepatterning the scribelines. With this method, further improvements can be achieved. Trenches with a width of 5 µm and a depth of up to 50 µm (which is sufficient to separate ultrathin chips) can be achieved with anisotropic dry etching. Using dicing by thinning together with etching gives several additional benefits:

• Parallel processing.
• Savings in silicon area, especially for small die sizes.
• Ideal chip edges improve fracture strength.
• Rounded chip corners enhance mechanical toughness.
• Non-rectangular die layouts are possible.

Unfortunately, applying an etching process to separate commercial wafers is not straightforward, because scribelines usually contain test circuits or process control modules, which cannot be etched in a simple way. Therefore, wafer layout has to be adopted to use the dicing by thinning concept together with trench etching.

Three-point bending tests with thin silicon samples have been carried out to measure the effects on mechanical stability. To eliminate geometrical dimensions of the samples, breaking force is transformed into breaking stress using the relation s=3/2·F·l/(w·t²), where s is maximum stress at force F for a sample with length l, width w and thickness t.

Experimental data shows that, for normally sawn samples, breaking force does not depend much on etching process. This indicates that fracture mechanics is clearly dominated from the sawn edge. Dicing by thinning removes these cracks, resulting in a higher fracture strength. Data also shows that breaking stress remains nearly constant after etching ~20 µm silicon. Etching more silicon leads only to minor improvements. In this area, variation of fracture is rather high, which can be explained by a different fracture mechanism — instead of breaking with one crack in the middle, the sample splinters in many fragments. This behavior is also an indication for the absence of surface irregularities.

It can be concluded that grinding damage extends ~15-20 µm into bulk silicon. The clearly larger bendability for samples fabricated with the dicing by thinning process demonstrates the efficient removal of cracks at the chip edge.

The most important feature of ultrathin silicon is the bendability in a wide range. Therefore, such ICs are for integration onto flexible substrates like polymer foil or paper. Such systems can be produced with reel-to-reel equipment, which is an emerging way to assemble electronics economically in high volume. Generally, face-up or flip-chip mounting is possible for die placement. Both techniques differ in many aspects from assembly of ultrathin chips.

Die bonding of thinned chips requires much more precise dosing of adhesive compared with conventional die bonding. The reason is that too much adhesive leads to inappropriate high die bonds. Because of low chip height, the risk for contamination of the bonding tool or the chip surface is quite high.

5. Cross-section of silver-filled polymer paste printed across the edge of a 20 µm thick chip.

6. Isoplanar contacts with laminated thin chip. Vias are opened by laser ablation.

Low topography of mounted thin chips can be used not only together with thick-film technology, but also with thin-film technology. Today, processes are developed to integrate thin ICs directly in thin-film multilayers.

Flip-chip assembly can be used for both low and high pin counts. For thin chips, the following consideration has to be taken into account: Among different flip-chip techniques, the only adequate methods are those that keep the assembly height low, otherwise the advantages of thinned chips are reduced. This demand rejects all methods that use high bumps (e.g., solder bumps) on substrate or chip.

7. Cracks resulting from flip-chip bonding using too high of a bonding force.

For flexible applications, flip-chip assembly with anisotropic conductive adhesive (ACA) is best suited. To carry out this technique, IC pads are electroless-plated with nickel/gold. The height of these bumps is only 2.5 µm — just to make them higher than chip passivation. Assembly is done using ACA containing gold spheres with a diameter of 5 µm. Bonding pressure is 0.1 N/mm², bond temperature 180°C for 60 sec. After bonding, adhesive is finally cured in a furnace at 150°C. With these parameters, test chips with a size of 10 × 10 mm are mounted on a flexible circuit with copper conductors. The mounted test pattern forms a chain of 88 flip-chip contacts, whose resistance was measured to be 17 V. Taking into account the conductor resistances of the chip and substrate metallization, a contact resistance well below 100 mV can be deduced.

Thermomechanical reliability has been tested by temperature cycling using the large 10 × 10 mm chips described above. No failures could be detected for more than 1000 cycles between -40 and 85°C. At one test sample, the resistance of the flip-chip contact chain has been monitored, and data show no degradation during the test.

Further investigations are made with RFID labels, which are made of 25 µm thin transponder ICs mounted on 50 µm thick polyimide foil. Silver-filled polymer paste and etched copper are used as coil metallization. Both isoplanar and ACA flip-chip methods are used for interconnection. These samples are aged by thermal cycling (-40/85°C) and humidity storage (60°C/93% RH). Reliability of these labels is still under investigation. Early data confirm thermomechanical stability of the assembly but indicate that ACA contacts with pure copper are susceptible to degradation. Absence of this effect for silver metallization suggests that the origin of these failures is not mechanical fatigue, but degradation of the copper/ACA contact interface.

Ultrathin silicon will find its way into many fields of microelectronics. For packaging, ultrathin ICs offer new and advantageous assembly techniques. Their low thickness permits new wafer separation methods with enhanced fracture strength and flexibility. Low topography of mounted thin chips offers direct integration in substrate manufacturing with both thick- and thin-film technology. Isoplanar interconnection methods are possible, as well as flip-chip mounting. Both are an ideal method for manufacturing low-cost systems in high-volume production lines. Because of their flexibility, ultrathin chips also support reel-to-reel manufacturing with foils or paper as substrate.