Energy Contamination in Low-Energy Implantation

The ideal mode of operating any ion implanter is the "drift mode," in which all the ions are extracted at the final implant energy. For example, for a 5 keV implant performed in drift mode, the ions are extracted from the source at a potential of 5 kV and delivered to the wafer. However, as implant energies drop and reach levels of 2 keV and lower, the drift mode starts to face a significant loss in beam current at the wafer because of space charge limitation of these low-energy beams leading to low extraction and poor transportation efficiency. The low beam currents lead to a sharp drop in productivity levels, which are not suitable for high-volume manufacturing.

To address the issue of decreasing productivity at low energies, decel mode is becoming the preferred approach for low-energy ion implantation. In this mode, ions are extracted at much higher potentials than the desired energies to draw higher beam currents from the ion source, and are decelerated electrostatically to the desired low energy just before they reach the wafer. A consequence of decel-mode operation is the introduction of energy contamination (EC) caused by dopant ions that are neutralized by charge exchange with the background gas and collisions prior to deceleration. These neutralized dopant atoms cannot be decelerated and hence arrive at the wafer with higher energy. The contamination resulting from these higher-energy atoms manifests itself in the source/drain extension (SDE) doping profile as a deeper tail, thereby affecting SDE junction depth and transistor characteristics.

For everyday use of decel in high-volume manufacturing, it is necessary to keep energy contamination to a minimum. This plays a critical role in the design elements of the ion implanter for decel-mode operation. Shortening the neutralization path length and improving the vacuum in the beam line are some of the traditional approaches used to minimize contamination. Novel approaches that go beyond these methods are required to further reduce energy contamination. The magnitude is measured by the percent dose (in atoms/cm²) of the unintended higher-energy contaminant fraction of the total implant dose.

Typical low-energy depth profiles, with energy contamination as measured by SIMS, exhibit two distinct features: a shallower portion from the majority fraction of ions implanted at the prescribed energy, and a deeper one from the smaller fraction of the neutralized higher-energy contaminant ions. Depending on the design of the ion implanter for a given beam current, energy contamination can range from 0.3 to >1% of the total implanted dose.

PMOS devices for the sub-90 nm geometry nodes require high doping concentrations in the channel to suppress depletion at the SDE junction, which is critical to suppress short channel effects and control sub-threshold characteristics of the device. The 2002 International Technology Roadmap for Semiconductors (ITRS) dictates that channel concentrations will exceed 1.0 × 10¹⁹cm^-3 at 90 nm and beyond in order to keep the depletion width limited to one-quarter the effective channel length (L_eff).¹ In such high-concentration channels, the effect of energy contaminant of the decel implant on the SDE junction depth is not significant because the tail region of the profile is immersed under the high-concentration background channel doping. Nevertheless, it is to be expected that this contamination will counter-dope the background (halo/pocket) doping by an amount proportional to the magnitude of the contaminant dose.

As an example, for 1% of 3 keV contamination in a 500 eV, 1.0 × 10¹⁵ cm^-2 boron implant, the dose of the 3 keV tail equates to 1.0 × 10¹³ cm^-2. This is less than the effective dose of halo/pocket underneath the SDE junction, which is typically mid-10¹³ to high-10¹³cm^-2. However small, this still leads to a reduction in halo/pocket concentration by counter-doping. This in turn will result in a shift in device characteristics such as lowering of the threshold-voltage (V_t), increase in off-state current (I_off) and increase in drive current (I_ds) as reported.²

This shift alone is not a major concern because device parameters can be recovered to the target values by tuning other process parameters such as channel or halo/pocket doping levels. The question is whether decel-mode implantation for the SDE with a low and controlled amount of energy contamination can result in equivalent device performance merits as produced by drift-mode implantation. This is important because performance merits of the device are just as critical as are the productivity merits in CMOS fabrication. Ideally, one benefit is not acceptable at the expense of the other. This work investigates the effects of energy contamination in PMOS structures from the device performance merit perspective.

1. Process flow used in the simulation.

A 500 eV boron SDE implant with a dose of 1.0 × 10¹⁵ cm^-2 was simulated using the Monte-Carlo method. Depending on the design of the implanter, such low-energy implants for SDE are typically performed in decel mode with decel ratios in the range of 2:1 to 6:1 with respect to the final energy. For this simulation, 3 keV energy contaminants were added to the 500 eV SDE implant in amounts of 0-5%.

The as-implanted dopant depth profiles under different contamination conditions for the same decel ratio are shown in Figure 2. Also shown is the background channel concentration. As evident here, the tail regions of the profiles with <3% energy contamination are submerged in background halo/pocket doping. The tail regions of the profiles with >3% contamination start to extend above the background channel doping, which leads to a significant change in the SDE junction depth. The junction depths for all these conditions after an RTP anneal are illustrated in Figure 3 for both devices under discussion.

2. As-implanted dopant depth profiles for a 500 eV boron implant under different conditions of energy contamination.

3. SDE junction depths after an RTP anneal for various conditions of energy contamination.

The combined effects of increased SDE junction depth and counter-doping of halo/pocket due to energy contamination lead to lowering of PMOS threshold voltage: V_T0, measured with 0.05 V drain bias; V_TH, measured with drain bias at V_DD; and V_TS, saturation threshold voltage. All three V_th parameters exhibit the same declining trend as shown in Figure 4 , suggesting that the saturation drain current (I_dsat) and off-state current (I_off) characteristics could have shifted as well. This shift in characteristics is consistent with what would be expected if the SDE implant were performed in decel mode. This means that the energy contamination is either leading to a deeper SDE junction, a counter-doped halo or both.

4. Threshold voltage behavior as a function of energy contamination in the SDE implant.

However, since the direct and most eminent effect of energy contamination results from the dilution of background channel doping, the characteristic device shift can be recovered by replenishing the background doping. The simplest way to accomplish this is to increase the halo/pocket dose without adding any implant steps. From a threshold voltage aspect, the iso-threshold line between the halo dose and contamination has linear characteristics for the range of contamination employed in this simulation (Fig. 5a ). The iso-threshold contour plot suggests that the effect of 1% contamination can be compensated by 2.5% or 1.67 × 10¹² cm^-2 of additional halo dose (Fig. 5b ).

5. Iso-threshold voltage contours between energy contamination and halo doping (a), and iso-threshold halo adjustment employed in the simulations (b).

6. Illustration of device behavior with energy contamination and halo compensation. EC moves the Ioff-Idsat characteristics in direction (a). Halo/pocket compensation shifts the characteristics in direction (b). Combined effect of energy contamination and halo/pocket compensation results in migration of the characteristics in minor departure toward direction (c).

7. Ioff-Ion characteristics for 45 and 32 nm devices under various conditions of energy contamination and halo doping.

8. Source-to-gate overlap capacitance behavior with and without halo compensation of EC.

A pictorial illustration of this behavior is shown in Figure 6 . The extent of this departure is largely dictated by the amount of contamination in the SDE implant and hence the amount of halo compensation. Thus, it is very important to note that energy contamination, though acceptable, must be controlled very precisely to within certain limits.

Simulation results in Figure 7 show the effects of the magnitude of energy contamination (up to 5%) with the associated iso-threshold adjustments of halo/pocket doping. However, for typical contamination levels of <0.5% on a well designed implanter, the degradation in device characteristics is minimal for both geometry nodes: For the 45 nm node, we observe ~1.3% increase in I_off and ~0.2% loss in I_dsat; for a 32 nm node device, these values are 0.5% and 0.4% in the same order as shown in Table 2 . Compared with conventional variations in device characteristics in a real manufacturing environment, such small shifts in device characteristics are almost insignificant.

To examine the effects on AC performance merits, source-to-gate overlap capacitance was also examined. As expected, increased energy contamination leads to more overlap of SDE to the gate. However, when halo/pocket doping is properly compensated, the overlap capacitance can be maintained constant (Fig. 8 ), suggesting that there is no more performance penalty other than a minor and tolerable departure in I_off-I_dsat characteristics.

With SDE energies dropping to sub-keV levels and declining productivity for such implants, decel-mode operation is the preferred approach for low-energy applications. The effects of energy contamination in decel-mode implants have been examined from a device performance perspective. The results demonstrate that, as long as contamination can be controlled to <0.5% levels, its impact on device performance is minimal. However, simulation results also show that excessive energy contamination can have detrimental effects on device characteristics.

It is therefore necessary to precisely control the energy contamination in decel-mode operation. To meet this requirement, novel approaches extending beyond the traditional methods of shortening the neutralization path length and improving vacuum are required in the design of low-energy ion implanters. Dual-magnet beam-line design coupled with traditional methods is one innovative solution to meeting the requirements.