3-D Chip Scale With Lead-Free Processes

IBM introduced flip-chip technology in the 1960s as the solder-based controlled collapse chip connection (C4) process. Now there are several techniques for attaching unpackaged ICs to substrates. Several companies use flip-chip processes to produce miniaturized turnkey electronic assemblies for medical implants, microminiature wireless devices, and a host of other applications.
 
Generally, it is a good idea to match an end-product application with the appropriate flip-chip technology, particularly when purchasing a miniature circuit package from a contract manufacturer. Recent innovations in flip-chip processes and 3-D chip-scale packaging allow unprecedented levels of miniaturization and reliability. For demanding applications where extreme miniaturization, reliable performance and exceptionally long life are crucial, a flip-chip process review should focus on chip bonding techniques with thin flexible substrates.

Three critical criteria define project miniaturization. First, the degree of reduced size can significantly increase a product's usefulness and market acceptance, especially in medical, telecommunication, aerospace and military applications. However, shrinking an electronic product involves trade-offs between size, manufacturing methods and cost.

Second, among applications that support the cost of miniaturization, high product reliability is a critical element. Appropriate miniaturization techniques allow reductions in the total number of connections, elimination of wire leads, and/or shorter lead lengths. All these steps reduce inductance, improve power consumption and lower operating temperatures. The ultimate result is higher overall product reliability.

Third, make/buy decisions are often associated with producibility issues involving circuit density, printed wiring substrate characteristics, component availability, production steps, economical manufacturing volumes, ability to automate processes, time-to-market and costs.

Many compatibility problems revolve around IC and substrate connectivity issues that are critical when size reduction, higher frequencies, and power dissipations enable product success. For instance:

• Pad arrangement becomes increasingly critical as chips shrink. A few misplaced pads can require longer, more convoluted PWB trace routings that affect capacitance, inductance, resistance, power consumption and crosstalk.
• Pad metallurgy may be incompatible with soldering, metallic bumping or wire bonding required in the desired miniaturization technique.
• Pad pitch might be excessively tight, increasing the PWB cost and increasing the chance of short circuits during manufacture.

Besides compatibility issues, flip-chip connection and bonding processes greatly affect the level of miniaturization possible, and the long-term reliability of the end product.

Flip-chip technologies can be characterized by contact method, substrate and assembly. Typical processes for surface mounting flip-chips to PWBs are: (a) screened bumps plus conductive adhesive gluing, (b) tin/lead bumping plus reflow soldering, or (c) gold electrodeposition bumping plus thermocompression bonding. Depending on the specific process, additional steps may be required, such as under-bump metallization (UBM) of the die, thereby adding steps and costs. The gold-on-gold stud bump process does not require additional UBM on the die, which reduces costs and time-to-market.

Solder flux issues are present with tin/lead bumping and reflow solder flip-chip attachment. Flux cleaning is advisable because a flux contaminant at or near a bump may cause a void, and subsequently a space for the solder bump to flow.

Also, temperature coefficient of expansion (TCE) mismatches between die, substrate and conductive adhesives can be a major problem. The severity of the problem grows with larger chips, high-expansion substrates and lack of co-planarity between substrate and die connection points.

In structures connected by solder bumps, different rates of expansion induce relative displacements during temperature cycling. Often, induced axial strain is neglected, because it is deemed to be small for small die. However, axial strain can be significant in a large die, necessitating a separate underfill to avoid large deflections. Still, large underfill variations contribute to proportionally large variations in product reliability due to solder fractures and creep problems, even within the same production lot. To avoid delamination and early solder connection failures, the underfill must be uniform, without voids, and have good adhesion to both surfaces (die and die carrier) as well as to the solder connections.

TCE considerations also apply to screened bumps using conductive adhesive attachments, which also require an underfill. The dielectric continuous phase of the bonding material must maintain a certain amount of tensional strain on the two adherents so the conductor interfaces (bumps and PWB connection pads) are kept in contact. If the polymer expands at a higher rate than the conductor, which is often the case, the pressure contact connection can open.

Furthermore, electrical connections with a conductive adhesive take place through a monolayer of conductive particles. These particles typically are <1 mil in diameter, so in rigid systems the coplanarity of two mated surfaces must be less than this dimension to avoid an open circuit. Ideally, a composite adhesive should have the same TCE as an adjacent dielectric, which can be more easily achieved if there are no conductive particles in the adhesive. This calls for a different attachment approach.

Finer contact pitches are limited by substrate characteristics. Generally, finer pitches are possible with flexible substrates. One reason is the ratio between the thin flexible PWB and microvia holes that interconnect each substrate layer. It is difficult to build a thick PWB with microvias. Additional plating problems occur within the via holes when the substrate thickness is more than 5× the diameter of the hole. When a given circuit design requires traces and spaces of <2 mils, a finished via hole diameter should be equal to this dimension, and the PWB should be no thicker than 10 mils. Otherwise, PWB real estate is compromised. Another important benefit of thin flexible substrates is greater versatility in packaging shapes and sizes through folding or bending.

Depending on the miniaturization method, the chip may be prepared on or off the wafer with additional metallization or pad redistribution layers to make it compatible with assembly processes. Chips intended for solder and conductive adhesives require preparation that can best be performed during wafer fabrication. A flip-chip that uses non-conductive adhesive requires comparatively simpler metal bumping of IC contact pads, which can be performed on whole wafers or individual ICs. Thus, solder and conductive adhesive techniques are better suited to larger production runs, while non-conductive adhesive techniques work well for prototyping and small to medium production runs.

Table 1 presents the salient characteristics of the three main flip-chip assembly processes.

* Thermoset adhesives usually require a post-bake after bonding for maximum performance.

Gold stud bump ball connections and adhesive bonding processes avoid many of the problems associated with solder. Being essentially mechanical processes, they lend themselves to automation techniques that increase productivity. However, some production procedures may still require well-trained, creative operators for manual assembly. In any case, these processes offer a good deal of flexibility for use with most sizes and types of ICs and substrates.

Generally, gold stud bumps can be applied with automated gold ball bonding equipment to either an uncut wafer or single die. Unlike other flip-chip processes, the gold stud bumps can be applied without any special UBM preparation of the wafer or chip, like the stud bumps illustrated in Figure 1 . Chip bonding adhesives typically are applied to the IC mounting area of the PWB with a screen-printing process.

1. Gold-on-gold stud bumps for flip-chip connection. Inset is a close-up of the bumps.

Processes for connecting a flip-chip to the PWB can range from manual to automatic, depending on the bonding system, connection pitches, etc. In automatic and semiautomatic processes, patented or proprietary equipment is used to align the die stud-bumps and PWB bonding pads before pressure is applied to collapse the bumps onto the pads. Localized heat is then applied to cure or set the adhesive in less then 10 sec. The adhesive bonding system can have a significant effect on production throughput and the reliability of connections. The final result is a pure gold-on-gold connection without contamination between the die and substrate.

A low-modulus, non-conductive thermoplastic adhesive allows the polymer to take up the strain produced by differential thermal expansion. Thermoplastic adhesives are pre-polymerized films (or pastes) that are softened by heating to a bondable state. This means that very rapid assembly is possible. Just heat, crush the IC stud bumps on the bonding pads and cool. Typical bonding parameters are:

• Pressure/bump: 50-80 g
• Temperature: 150-250°C
• Adhesive cure time: <10 sec
• Alignment: ±5 µm (±1 µm optional)
• Planarity: ±5 µm (±1 µm optional)

Thermoplastic non-conductive pastes exhibit low outgassing, since there is no chemical reaction during or after bonding. Therefore, they can be used in hermetically sealed units. Their performance is comparable to the workhorse thermoset epoxies, but they can be repaired, allowing die replacement. This is especially important for MCMs with high die counts, which must have die replacement capability to be economically viable.

With good equipment design, all connections can be completed in one automated operation, with connection pitches as fine as <100 µm on flex substrates as thin as 25 µm. This requires some mechanism for adjusting pressure on individual stud bumps to make up for planarity variations across the substrate and bonding pads. The larger the number of connections, the more important these features become.

Of course, miniaturization design must support economical attachment of other SMT components that are as small as possible. With robust flip-chip and SMT component connections, plus highly flexible substrates, extreme miniaturization is possible. This includes rolling or folding the assembled PWB into a 3-D, multilayer package, as in Figure 2 .

2. Construction of a 3-D CSP assembly.

Table 2 lists some key performance specifications for well-constructed flip-chip assemblies. Again, there are substantial variations based on bonding processes and chip characteristics.

*Requires qualification for specific applications

Picking the right flip-chip technology can be crucial for a profitable end product, but judgment is still required in deciding how much miniaturization is practical. For example, existing technology could easily support further miniaturization of cell phones, but the resulting handset would be more expensive, difficult to use, and lack the power needed for acceptable performance. On the other hand, the higher cost of extreme miniaturization may be tolerable in a medical implant, because it represents a small portion of the total treatment expense.