NIST Develops New Superfill Model for Metal

Copper interconnects are formed by a damascene method where holes and trenches are first cut into the dielectric and then filled with copper. After dielectric etch, a diffusion barrier is formed, then a seed layer of copper is sputter-deposited by physical vapor deposition (PVD). The copper is then electro-plated onto this seed layer, eventually filling the holes and trenches. This is followed by a final CMP step to level off the copper.

Through the use of various additives to the electroplating solution, it's possible to achieve what is known as superconformal deposition, or "superfill." With superfill, metal is preferentially deposited from the bottom up, permitting the bottom surface to rise before the side walls close off. This eliminates voids and seams that can cause high resistance and other problems.

Achieving superfill while also meeting all of the other requirements of a successful electroplating process (i.e., fine-grain films with low resistivity) can be a fairly complex process, however. Fortunately, thanks to work at the National Institute of Standards and Technology (NIST, Gaithersburg, Md.), there is now a software model that includes a quantitative description of electrolytes, catalysts and interactions among these and other ingredients involved in the bottom-up superfill deposition. Using this predictive model based on a curvature-enhanced accelerator coverage (CEAC) mechanism, semiconductor manufacturers can simulate the influences of different additives on feature filling and optimize their electroplating processes. The NIST-developed software is available for free at www.ctcms.nist.gov/~wd15/superfill/superfill.html. Users are requested to note the NIST origin of the code and the website address in presentations that incorporate results generated using the downloaded code.

Uniform, bottom-up filling of trenches with copper is key to achieving defect-free interconnects. The top image shows two trenches, about 50 nm wide at mid-height, after 7 sec of copper electrodeposition. The bottom image shows trenches lined with a tantalum/ruthenium barrier. (Source: NIST)

Focused initially on copper, the NIST team has since demonstrated superfilling with silver, which is a superior conductor to copper. They also have shown how the CEAC mechanism can be applied to surfactant-catalyzed chemical vapor deposition (CVD) of copper, a potential alternative to the electrodeposition process.

The team also used its deepened understanding of superfilling to devise a method that results in more stable electrolytes and permits filling of trenches and vias with greater aspect ratios. These desired outcomes are achieved by applying the reaction-accelerating catalyst directly to the patterned silicon wafers, as opposed to the current practice of incorporating the catalyst into the copper-plating solution.

In soon-to-be-published research, the team eliminates the need to seed wafers with sputtered copper films prior to superfilling, a significant process simplification.

For additional information on wafer processing, go to www.semiconductor.net/wafer