3-D Packaging – Nowhere to Go but Up

During the 1990s, semiconductor packaging made steady progress on new technology and process development, culminating with a burst of creativity near the turn of the century corresponding with technology's booming bubble years. First, the ball grid array (BGA) replaced package leads — arrayed solder bumps reduced size, increased I/Os, and enhanced performance and process, yet were produced at an affordable cost. Next came the chip-scale package (CSP), offering refinements such as higher I/O, further performance upgrades, easy assembly, reasonable cost, full reliability, and a remarkable package shrink to at or near die size. Apparently, engineering had achieved the ultimate package, with X and Y dimensions nearly identical to bare die size.

Now, wafer thinning technologies that produce die to 100, 75 and even 50 µm, shift today's focus on the Z dimension and package stacking. In fact, through wafer thinning, many stacked packages available today present multiple packaged die at the same or less vertical height (~1.2 mm) as yesterday's BGAs and CSPs. It appears that the Z dimension is the final frontier and silicon packagers are exploring a multitude of stacked package solutions.

In talking with various packaging suppliers, enthusiasm for 3-D seems to run high. However, several issues must be resolved to achieve widespread adoption. Moreover, with so many variations already available and many more to follow, the likelihood of any single monster solution seems slim. Much like the BGA and CSP predecessors, a multitude of stacked package flavors appears imminent. But that will be good news, since each variety will fit an appropriate niche application.

3-D package considerations will include laminate or flex circuit substrates, wire bond (edge or center pad), flip chip, conductive adhesive or combination interconnections, stacking pyramid style, overhang, foldover or others, using mixed technology stack with flip chip and lead-free or eutectic solder balls.

Much like the BGA and CSP predecessors, a multitude of stacked package flavors appears imminent. (Source: Amkor Technology)

On the die vs. package stack issue, it appears most applications will favor package stacking. When comparing die stack to package stack, one primary distinction centers on the fact that die stacking raises known good die (KGD) issues whereas package stacking has the advantage of already tested die. Another distinction is that qualified packages can accommodate multiple suppliers without requiring significant new development time and cost.

Clearly, established BGA and CSP infrastructure has helped propel 3-D package development. Although we are in the early stages of technology adoption and many challenges remain, customers will soon expect a 3-D package solution for many mobile wireless systems. Each application may dictate a unique packaging solution, but with so many stacked package innovations already available, it's likely the right fit may just come off the shelf.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly