Carbon Nanotube Interconnects: Untangling the Noodles

The semiconductor industry now employs aluminum or copper for on-chip interconnects, but scientists at the NASA Ames Research Center (Moffett Field, Calif.) have another idea: carbon nanotubes. Carbon nanotubes, which are cylindrical fullerenes, are attractive because of their extraordinary mechanical properties and unique electronic properties, including exceptional current carrying capacity.

In one set of experiments, multi-walled carbon nanotubes (MWCNTs) did not degrade after 350 hours at current densities of 10¹⁰ A/cm² at 250°C. The main problem is how to make use of a material in semiconductor manufacturing that often forms like a web during growth, and when deposited on substrates and inside trenches, appear as "noodles." The hoped-for ballistic transport of electrons and high conductivity is unlikely to happen in entangled nanotubes.

At Ames, researchers are working to untangle the noodles by developing a process where MWCNTs are grown using PECVD. This is followed by gap-filling the spaces between the MWCNTs with SiO₂, and by CMP to provide a flat-top surface for depositing the top metal line. In work presented at the International Interconnect Technology Conference (IITC) and published in Applied Physics Letters in April, Jun Li and fellow researchers described the process they developed.

A silicon (100) wafer covered with 500 nm thermal oxide and 200 nm chromium (or tantalum) lines is used to deposit 20 nm thick nickel as a catalyst. Ion-beam sputtering is used to deposit nickel on patterned spots for local wiring or contact hole applications; for global wiring, nickel can be deposited as a 20 nm thick micron-scale film. Then PECVD is used to grow a low-density MWCNT array by an inductively coupled plasma process or dc plasma-assisted hot filament CVD as reported previously. Each CNT is vertically aligned and freestanding on the surface. Such CNT structures are not possible by thermal CVD, but are produced by PECVD due to the electric field normal to the substrate. Next, the free space between the individual CNTs is filled with SiO₂ by CVD using tetraethylorthosilicate (TEOS).

This is followed by CMP to produce a CNT array embedded in SiO₂ with only the ends exposed over the planarized solid surface. The CMP process removes the excess SiO₂ and breaks the CNTs, resulting in a planarized SiO₂ surface with only the very ends of the CNTs exposed.

The future of interconnects might include carbon nanotubes, such as those shown here, which have very high current carrying capabilities. (Source: NASA Ames Research Center)

Lithographic patterning can be used to control the location of MWCNTs as shown in the Figure, where e-beam lithography was used to define the spots. The Figure shows individual MWCNTs wrapped with SiO₂, about 3 µm tall. The CNTs extend ~30-50 nm above the SiO₂ surface, likely due to their better mechanical resilience. Bright contrast indicates conformal SiO₂ wrapping around each individual CNT even in the portion that protrudes.

This approach completely eliminates the etching step associated with damascene processing, and thus the need to create high-aspect-ratio contact holes. The approach uses the sequence of deposition of nanotubes, deposition of SiO₂, and CMP instead of etching-deposition-CMP. Very high-aspect ratios are readily formed and TEOS CVD of SiO₂ around the nanotubes does not pose the same level of void-free filling concerns commonly encountered now.

The NASA researchers say that CNTs embedded in a SiO₂ matrix would withstand current densities far higher than that desired by the International Technology Roadmap for Semiconductors (ITRS). Although the measured resistance of a single MWCNT (as fabricated) is more than an order of magnitude higher than the theoretical value, the use of a compact bundle or increasing the number of MWCNTs in contact may already be sufficient for global wiring.

The researchers believe there are several reasons for the observed resistance and possible ways to reduce it. First, the contacts to nanotubes to date are not perfect. Typically, metal contact has always been to the sidewall of CNTs. In the NASA approach, contact is made to all the shells, which is favorable for interconnect applications. Theoretical studies show that the length of contact between the metal and the nanotube is critical for low resistance; the conductance drops dramatically when the contact length is <10 nm. In practice, a catalyst metal such as iron, cobalt or nickel may be deposited on top of the MWCNTs before deposition of the top metal line. Also, thermal annealing in the presence of the transition metal can improve the electrical contact between CNTs and metal lines.

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