Time to SPICE Up Interconnect
Alexander E. Braun, Senior Editor -- Semiconductor International, 9/1/2003
While the industry, like Hamelin's children, continues to dance skirting the precipice as it follows the Pied Piper of Moore's Law, new materials and processes are being researched and rapidly brought in to cope with the problems brought by shrinks now approaching atomic levels. Silicon on insulator (SOI) and strained silicon are viewed as candidates for the improvement in transistor performance, and copper and ultralow-k materials are being brought into the mainstream.
What many seem to be missing is that the keystone problem we face in the pursuit of Moore's Law is that we are already at the point in state-of-the-art logic at which IC final performance is no longer determined by the transistor, but by the interconnect. This is a serious design issue that forces the ongoing work on the design of copper interconnect to keep up with the additional meteoric progress being carried out at the front end. The dilemma is that producing a layout of interconnect at this level today is more akin to a mixture of black magic, empirical experience, and child-like faith than to the exact science that it ought to be.
Simply put, the problem is that there are no equivalents of the SPICE models for interconnect. We do not lack models that have been produced to describe the behavior of a transistor; these are extremely sophisticated as well as proven and mature. However, we still do not have the equivalent modeling capability in interconnect. This deprives the design engineer of an increasingly necessary and very useful tool.
Nobody in the industry doubts for the briefest instant that there would be a tremendous gain in capability were it possible to gain a greater understanding of how interconnect behaves from an RC delay perspective. This would give the design engineer far more than just empirical experience on which to determine the trade-offs that need to be made. This is a ready-made opportunity for the CAD world to come up with tools that will allow us to produce far more sophisticated interconnect layouts.
Diagonal interconnect (i.e., X Architecture) is an initiative that has been discussed for the past two years or so. This is a first, simple step in what could be done to bring interconnect layouts into the modern age, providing the same modeling capabilities that today exist for what happens on the silicon with the transistor. We desperately need to raise to a higher awareness the dialogue between unit process development and interconnect layout. We are now — not in some future time four or five nodes away — approaching the fundamental limits of what we can do with interconnect technology. The fundamental limits about what kinds of dielectric materials are integrable are in sight.
By the time we attain the 32 nm technology node, we will have reached copper's fundamental limits. All our designs will experience a rapid increase in resistivity because of electron scattering in these very small features. We are speeding at full throttle toward a formidable interconnect brick wall. If we wait until we splatter against it before we begin doing more than just thinking about how we can maximize interconnect performance based on layout, then it will be too late to do the work on the design side.
There are some ongoing preliminary dialogues and exchanges that may eventually yield such design fruits. However, as is so often the case with these matters (standards committees, for example), they proceed like the mills of the gods: They grind very slow and exceedingly small, probably much smaller than what is needed to get some real-world design software. We can no longer afford delays — the technology is approaching quantum levels at quantum leaps. These dialogues must be elevated and speeded up. Links must be firmly established between the designers of interconnect and the process people, and they must find out, quickly, how best to cooperate.
If a productive dialogue is established now, we can probably add another 10 years to that lifetime. As things stand, it may take us as much as 20 years to get to the next generation of ICs: carbon nanotubes or the molecular transistor. We must extend silicon technology until then.
