Conference Report: Plasma and Plasma-Induced Damage 2003

Held for the first time in Europe, the Eighth International Symposium on Plasma- and Process-Induced Damage (P2ID) brought together researchers from Asia, the United States and Europe in April. Hosted by Altis Semiconductor in Corbeil-Essonnes just outside of Paris, the conference was directly sponsored by the IEEE for the first time. This symposium has provided a forum for interaction between process developers, tool designers, electrical engineers, chemists and physicists investigating the unintended (and undesirable) consequences that sometimes accompany the processes used in modern semiconductor fabrication. Although many papers focus on charging damage, or electrical overstress that occurs during processing, many papers address damage that is more physical in nature. In this article, we review some of the work presented at this conference, and prognosticate as to the future directions of this research.

Arcing in plasma processes

Although much progress has been made in identifying and eliminating the basic causes of charging damage (such as global plasma nonuniformity and electron shading), sporadic events of relatively low frequency can continue to plague manufacturing lines long after the fundamental process has been shown to be nominally damage-free. At this conference, Ma et al. of Applied Materials¹ described several forms of arcing events and their prevention. The frequency with which arcing events occurs is affected by both the inherent plasma stability and the features on the wafer being etched. The plasma stability in turn is determined by the chamber design and the operating parameters. Some of the factors shown to exacerbate the frequency or arcing events were exposed metal patterns on the edge of the wafer, the degree of overhang of the wafer beyond the electrostatic chuck, and higher plasma density, by use of a magnetic field or a second rf source, for example (Table and Fig. 1 ). Surprisingly, chamber pressure did not have an effect on this arcing phenomenon, although work reported at this conference² and others^3-4 show fewer damage events with higher chamber pressure for deposition processes. This new line of research, involving rare events on thousands of wafers, will likely usher in a new direction of activity particularly suited to improved manufacturability under sporadic charging conditions.

(Source: Applied Materials)1

1. Etch chamber design characteristics that contribute to the frequency of arcing events.1

UV-Induced silicon nitride antennae

SiN is used in many places through the process sequence in a manner that leaves a nearly continuous film across the wafer. There is often an etch-stop layer below the contact, and then in copper metallurgy there is a nitride barrier layer associated with each metal level. Under conditions of intense irradiation such as may be experienced in the plasma environment, the SiN may become conductive. In principle, this film could protect against charging damage were it to be conductive enough to bleed current to the substrate. In other circumstances, this conductive film itself could function as an antenna. Authors from Philips⁵ report on such a case, in which the etch-stop nitride conducts charge to the transistor gate, which is then damaged. The authors show an antenna dependence of damage during contact overetch. This occurs prior to the deposition of any metallic conductive layer, and therefore the plasma current must be conducted to the gate through the SiN.

Physical damage

A number of papers addressed aspects of damage that were more physical, or perhaps chemical, in nature. Hook et al. of IBM⁶ reported that heavy fluorination of the gate polysilicon can result in the mechanical dissolution of the NFET polysilicon/gate oxide interface, and also modifies the nitrogen content of nitrided gate oxides, and increases the gate leakage. An interesting paper from Samsung⁷ showed the effects of the well-known gate notching effect on a low-power SRAM cell, specifically addressing which of the devices were most susceptible to notching, and then detailing the specific effects on the SRAM behavior. The gate notching was shown to result in an effectively thicker oxide on the pass transistor, with an accompanying increase in sub-threshold slope and a larger off-current, thereby compromising the critical leakage current of this low-power SRAM. This paper also shows that the static noise margin of the cell is adversely affected by the gate notching. Chan et al. of TSMC⁸ showed a correlation between physical substrate damage and loss during photoresist removal and drain current degradation, based on the chemistry of the strip process (Fig. 2 ).

2. Drain current degraded by surface damage from plasma treatment.8

Negative bias temperature instability

Research into the phenomenon of NBTI continues to be of interest. Scarpa et al.⁹ report how various processes affect NBTI. The water content of the etch-stop nitride was shown to significantly affect the threshold shift (Fig. 3 ). They also observe a substantial improvement with the introduction of fluorine. Chaparala et al. of National Semiconductor¹⁰ showed data on how critical NBTI can be in matched analog circuits. Although it has been shown before that PID (plasma-induced damage) can exacerbate NBTI and hot-carrier instability, an interesting observation is made,¹¹ in which NFET hot-carrier is unaffected by PID, but thick-oxide NBTI is increased. The authors note a correlation of NBTI with initial gate leakage, commenting that both phenomena may be related to trapped holes.

3. Profound changes in NTBI shift due to process changes. Recipe A and Recipe B are two different barrier nitride processes.9

Survey results

A survey was devised by Paul Aum of Spider Systems and distributed at the 2002 P2ID. In this year’s symposium, the survey results were published,¹² and a panel discussion was held to discuss some of the results. Among the more pointed responses, it was interesting to note that most respondents felt that tool manufacturers were in the best position to address the concerns of PID, but that integration and process engineers were actually expected to solve the difficulties. It is hoped that close cooperation between those that have the wafers (the process engineers) and those that have the tools (the equipment suppliers) may bridge this discrepancy. The survey respondents also indicated that the area of greatest concern for charging damage was with regard to the effect on analog devices, but as of yet there is little work reported in the literature on analog-specific problems. Although the survey indicates a preponderance of charging-related concerns, at least one-third of the damage issues experienced by the survey respondents are physical or chemical in nature.

Prognosis

It is generally agreed that, even if charging damage is lessened for oxide thicknesses below 2 nm, legacy power supply requirements will mandate that thicker, more damage-susceptible oxides be present for the foreseeable future. Fruitful research in the field of charging damage is likely to continue with regard to the efficacy and methodology of protection schemes, multi-terminal effects,¹³ arcing events and, of course, charging-free processing such as neutral beams¹⁴ or better tool and process design. The issues associated with chemical and physical damage may reach greater prominence with the emergence of new technology elements such as high-k gate dielectrics, strained silicon, and three-dimensional device structures¹⁵ and the increasing importance of the electrochemical phenomena known as NBTI. Work on these and other topics is expected to be presented at next year’s P2ID.

Returning to the United States in May 2004, the Ninth Annual Symposium will be held at Motorola Semiconductor in Austin, Texas. Updated information will be posted at the P2ID website, www.p2id.org .

References

1. S. Ma, N. Hanabusa, S. Shoji, M. Kutney, T. Detrick, B. Patada and R. Straube, “Backend Dielectric Etch Induced Wafer Arcing Mechanism and Solution,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 178.
2. S. Schulte, G. Dubois and D. Basso, “Gate Oxide Degradation due to Plasma Damage Related Charging During ILD Cap Oxide Deposition,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 95.
3. D. Cote, A. Stamper and S. Nguyen, “Process Induced Gate Oxide Damage Issues in Advanced Plasma Chemical Vapor Deposition Processes,” Proc. 1st Int. Symp. on Process- and Plasma-Induced Damage, Santa Clara, Calif., 1996, p. 61.
4. T. Hook, A. Stamper and D. Armbrust, “Sporadic Charging in Interlevel Dielectric Deposition in Conventional Plasma and HDP Deposition Systems,” Proc. 2nd Int. Symp. on Process- and Plasma-Induced Damage, Monterey, Calif., 1997, p. 149.
5. A. Cacciato, A. Scarpa, S. Evseev and M Diekema, “Charging Damage During Contact Etch Triggered by Increased Borderless Nitride Conductivity,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 20.
6. T. Hook, R. Kontra, J. Burnam and M. Lavoie, “The Effect of Fluorine in an Advanced CMOS Process With Triple (1.6/2.2/5.2 nm) Nitrided Gate Oxide,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 150.
7. S. Seo, S. Kim, W. Yang, J. Ju, J. Kim, S. Park, S. Kim and K. Kim, “Effects of Gate Notching Profile Defect on Characteristic of Cell NMOSFET in Low-Power SRAM Device,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 146.
8. B. Chan, B. Perng, L. Sheu, Y. Chiu and H. Tao, “Plasma Induced Substrate Damage in High Dose Implant Resist Strip Process,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 73.
9. A. Scarpa, L. Marwijk, A. Cacciato and F. Ballarin, “Effects of the Process Flow on Negative-Bias-Temperature Instability,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 142.
10. P. Chaparala, D. Brisbin and J. Shibley, “NBTI in Dual Gate Oxide PMOSFETs of Analog and Mixed Signal Processes,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 138.
11. E. Li, D. Pachura, L. Duong, S. Prasad and D. Vijay, “Plasma Induced Charge Damage and its Effect on Reliability in 0.115 mm Technology,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 69.
12. ”P2ID 2002 Industry Survey of Process-Induced Damage,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 108.
13. J. Mercier, T. Dao, H. Flechner, B. Jean and D. Oscar, “Process Induced Damage From Various Integrated Circuit Interconnection Designs -- Limitation of Antenna Rule Under Practical Integrated Circuit Layout Practices,” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 162.
14. D. Lee, M. Chung, S. Jung and G. Yeom, “Low Charging Damage SiO₂ Etching With a Low-Angle Forward Reflected Neutral Beam,“ Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 186.
15. T. Dao, “Process Induced Damages -- What Challenges Lie Ahead?” Proc. 8th Int. Symp. on Process- and Plasma-Induced Damage, Corbeil-Essonnes, France, 2003, p. 51.