SI CHINA     SI JAPAN
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

Copper Cap Reduces Leakage, Improves Breakdown Behavior

Laura Peters, Senior Editor -- Semiconductor International, 8/1/2003

Amorphous SiC-based dielectrics (α-SiC:H) are starting to replace SiN-based films as etch stop and copper capping layers in low-k dielectric stacks because of their lower k value, better etch selectivity with organosilicate glass (OSG) films, copper barrier properties and passivation properties. Recently, companies have begun optimizing these film stacks for specific integration with OSG films.

For instance, researchers from the National Chiao-Tung University (Hsinchu, Taiwan) and Taiwan Semiconductor Manufacturing Corp. (TSMC, Hsinchu) recently determined that a bilayer of α-SiCN (k~5) and α-SiC (k~4) can improve the time-dependent dielectric breakdown (TDDB) lifetime of copper damascene structures. In their latest work, Chiu-Chih Chiang et al. showed that leakage mechanisms depend on the ratio of the nitride to carbide thickness, but the breakdown field and TDDB exhibited little dependence on the thickness ratio and appears to be caused by breakdown of the bulk OSG dielectric.

In the copper damascene structure with varying thicknesses of α-SiCN/α-SiC bilayer, the large leakage current (Frenkel-Poole emission) between copper lines was attributed to the abundance of interfacial defects at the α-SiC/OSG interface. The tests used 0.12/0.12 µm comb capacitors with OSG, PVD TaN liners, ECD copper and SiCN/α-SiC bilayer of 50/2 nm, 45/5 nm, 40/10 nm or 30/20 nm, followed by PECVD of OSG for the M2 layer.

The researchers determined that the dominant leakage path in the copper damascene structure is electronic current through the bulk of OSG and/or the α-SiC/OSG interface (CMP-surface). Since the SiCN has a compressive stress and the OSG and α-SiC have tensile stress, in the case of thicker α-SiC films, the larger tensile force may generate more interfacial defects such as cracks, voids, traps or dangling bonds at the SiC/OSG interface.

For additional information on yield management, go to www.semiconductor.net/yield .

Email
Print
Reprint
Learn RSS

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

Related Content

 

By This Author

SPONSORED LINKS



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts
  • Videos

Blogs

  • David Lammers
    Views on News

    October 6, 2008
    IBM And The All-In Bet on High-K
    The debate about the worthiness of high-k/metal gate technology brought to mind what Japanese semico...
    More
  • Alexander E. Braun
    The Measure of All Things

    August 11, 2008
    Considering Beyond-CMOS Metrology
    Metrology has become one of the main pillars upon which the semiconductor industry bases its progres...
    More
  • » VIEW ALL BLOGS RSS

Podcasts

Videos

Advertisements





NEWSLETTERS
Plug in and get the latest SI news, trends and industry updates delivered free, directly to your inbox!

SI NewsBreak and Special Reports (Weekdays)
Wafer Processing Report (Monthly)
Lithography Report (Monthly)
Metrology Report (Monthly)
Clean Processing Report (Monthly)
Packaging Report (Twice Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites