Intel Looks to Triple-Gate Transistors, CDO Low-k

Intel Corp. (Santa Clara, Calif.) revealed new details of its tri-gate transistor design at the 2003 Symposia of VLSI Technology and Circuits in Kyoto, Japan, and said that the tri-gate transistor is moving from research to the development phase. Since originally announced last year, Intel researchers have successfully shrunk the size of the tri-gate transistor (measured by the gate length) from 60 to 30 nm.

"Our latest research indicates that the scalability, performance and excellent manufacturability of our tri-gate transistor makes it a strong contender for production as early as 2007 on our 45 nm process technology," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group. "The results place non-planar, 3-D transistor structures among the promising nanotechnology innovations that we will use to extend silicon scaling and Moore's Law well into the future."

Intel's tri-gate transistor employs a 3-D gate structure, like a raised plateau with vertical sides, which allows electrical signals to be sent along the top of the transistor gate and along both vertical sidewalls. This effectively triples the space available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more area. This gives the tri-gate transistor much higher performance than today's planar (flat) transistors.

Since originally announced last year, Intel researchers have successfully shrunk the size of the tri-gate transistor (measured by the gate length) from 60 to 30 nm. Intel’s tri-gate transistor employs a novel 3-D gate structure, like a raised plateau with vertical sides, which allows electrical signals to be sent along the top of the transistor gate and along both vertical sidewalls. (Source: Intel)

Intel says its tri-gate transistor is designed so it can be manufactured in high volume, a factor that will be key in moving it from the development stage into production. The tri-gate transistor design also addresses the growing current leakage problem the industry faces as CMOS devices are made ever smaller. Because of its unique structure, the tri-gate transistor's leakage is far less than that of a planar transistor of the same size. Intel has moved the tri-gate transistor design from research to the development phase, and experimental devices have been successfully manufactured at Intel's 300 mm wafer fabrication facility (Fab D1C) in Hillsboro, Ore.

In separate news, at another conference — the International Interconnect Technology Conference (IITC) — Intel described its next generation of interconnect technology for the 90 nm generation, and noted that it would used carbon-doped oxide (CDO) as the low-k material of choice. Intel researchers stated that all low-k ILD materials exhibit much weaker mechanical strength in every category — including modulus, hardness, adhesion and cohesive strength — than SiOF and oxides used in previous generations, but that CDO films with an intrinsic k<3 represented the best balance between performance and sufficient mechanical strength for packaging and reliability.

Intel's interconnect technology features seven layers of copper metallization/low-k ILD to boost interconnect performance over 130 nm technology. Progressive metal pitches are used for density and yield consideration with a minimum pitch of 220 nm at the Metal 1 layer to >1 µm at the Metal 7 layer. A via-first dual-damascene integration scheme is used for process simplicity and better design rule control. A simple single ILD/etch-stop stack is deployed on all layers for cost efficiency and better capacitance performance. M1 and M7 ILD stacks each are SiO₂/SiN, and the rest are CDO low-k ILD stacks. The primary roles of the oxide layers at M1 and M7 are to enhance the mechanical strengths of the entire interconnect stacks. The top oxide layer can shield mechanical and thermal stress that occurs during assembly and packaging. Secondly, the compressive stress of oxide layers serves as a clamp to balance the high tensile stress of CDO films.

Intel also reported that, with the technology scaling, via resistance increases dramatically because of scaled via CD. The via resistance can limit the interconnect performance and yield if not controlled. In the dual-damascene process, the via resistance is mainly determined by the barrier materials and via bottom barrier thickness, which is limited by the minimum sidewall barrier coverage.

A conformal barrier deposition technique, such as ALD, yields minimum via bottom barrier thickness. However, most of the ALD materials that have been developed so far exhibit high resistivities. Instead of ALD, Intel used an "improved" conventional barrier deposition process to improve the sidewall barrier coverage and to allow a reduction of via bottom barrier thickness and via resistance.

For additional information on wafer processing, go to www.semiconductor.net/wafer .