Low-k Webcast Reveals Roadmaps, Hurdles, Accomplishments

Semiconductor International's first technology webcast focused on one of the most controversial technologies of our time: low-k dielectrics. Its speakers, Katie Yu of Motorola, Wilbur Catabay of LSI Logic and Reinhold Dauskardt of Stanford University, described the pains and gains of bringing low-k dielectrics into production environments, combining low-k with copper, and the challenges encountered with first- and second-generation low-k dielectric solutions.

LSI Logic was one of the first companies to integrate a low-k film, taking the unusual path of integrating it with subtractive aluminum interconnects. "One of the biggest challenges was integrating tungsten plugs with the low-k due to damage to the low-k and thermal exposure during tungsten deposition," explained Catabay, director of advanced process module development of the Research and Development Group at LSI Logic (Milpitas, Calif.). He emphasized that early learning on 180 nm low-k (k=3.1)/Al eased the integration of second-generation low-k materials (k=2.8) ( Fig. 1). He showed electrical data that revealed 20-36% line-to-line capacitance improvement between HDP oxide and low-k ILDs with low carbon and high carbon content, respectively. LSI Logic has 180 nm Al/low-k in high-volume production, 130 nm Cu/low-k in full production, has qualified Cu/low-k (k=2.8) at 90 nm, and has the goal of integrating a k=2.2 material into 90 nm dual-damascene structures by the end of 2003.

1. At the 180 nm generation, this TEM shows good barrier coverage with 45 nm offset vias and low-k material (k=2.8). (Source: LSI Logic)

Yu, manager of the Advanced Interconnect Group at Motorola's Advanced Products Research and Development Lab (Austin, Texas) explained that her company used FTEOS (k~3.6) at the 180 nm node (six levels of metal), FTEOS at the via levels and a SiCOH material (k~3.0) at the trench levels for its high-performance 130 nm technology node (M7), but SiCOH at all levels for the 90 nm node (M8). Both the 180 and 130 nm processes are implemented on SOI devices with equivalent yield and reliability, including packaged device reliability, to FTEOS-based devices. Motorola has shipped more than 100,000 devices with low-k back-ends. Even the partial low-k SiCOH implementation at 180 nm delivers a 20% chip-speed improvement and lower power than FTEOS.

Catabay explained that, when incorporating copper lines with low-k, some of the reliability and yield problems encountered included copper extrusion, voiding in copper lines, leakage and delamination. "But by far the biggest problem the industry has seen has been stress voiding inside the via depending on the current flow," he said. His group developed models for stress migration and electromigration that take into account current crowding of copper ions in vias and delamination phenomena with different metal and dielectric barriers.

Due to the differences in thermal expansion properties between copper, low-k dielectrics and various barrier films that undergo multiple high-temperature processes, it is no surprise that multilayer film stacks of copper and low-k films are vulnerable to fracture and debonding (adhesion loss) during wafer processing and packaging. Through various projects, Dauskardt, associate chair of the Materials Science and Engineering Department of Stanford University (Stanford, Calif.), and his students are studying the effects of moisture and temperature on the rate of debonding and fracture of various dielectric materials, as well as the effects of processing on the reliability of thin-film patterned structures.

Dauskardt and his group use a four-point bending tool to measure thin-film adhesion energies at film interfaces. "We find that if debonds are present at the interface between the ILD and capping layer or in the ILD itself, when it is exposed to moisture content, the rate of debond accelerates dramatically." They drew a correlation between the rate of growth of the debond and the mechanical driving energy from either the imposed CMP load or residual stresses in the structure. For this reason, certain etch stop or capping layers can be chosen specifically to absorb some of these stresses. For instance, an organic polymer layer has the capability to slow cracking growth rates due to higher elasticity than, for instance, brittle low-k glass-like materials.

CMP processes have generally been optimized for maximum planarity while minimizing the effects of dielectric erosion and copper dishing. However, increasingly, there is a need to make the CMP process more compatible with low-k films. "Right now we use a hard mask, but this affects the overall k value, so we would much prefer low-k-compatible slurries," said Yu.

Mechanical properties such as density, modulus and fracture resistance generally become worse as air is added to any low-k dielectric. Thermal budget poses additional concerns. Finally, building reliability and yield into porous structures is an enormous challenge for the industry.

Yu highlighted the integration challenges needed to deliver reliable devices, including solving problems of resist poisoning, developing low-k compatible rework processes and maintaining as-deposited k values. Yu listed the Cu/low-k integration challenges as low-k materials development (ILD/Cu passivation); resist poisoning; low-k etch damage; compatible rework processes; low-k barrier compatibility; CMP planarity/low-k compatibility; trench sidewall profile control (taper); reliability testing; and fundamental low-k characterization/porosity control. She said that, to eliminate resist poisoning, they had to optimize resist selection, choose the best integration scheme and engineer the film stack. "Trench first, via last is less susceptible to resist poisoning than via first, trench last schemes." She expects that, with porous low-k films, barrier compatibility will become more of an issue.

2. Generally, mechanical properties worsen with increasing porosity. However, in some cases, toughness can be improved by 10× by porogen remnants that act as adhesion promoters. (Source: Stanford University)

One method of introducing pores to low-k films is to reactively blend a porogen material, volatilize it and then vitrify the remaining material. One such example is a 50% porous MSQ material. Dauskardt explained that, although most mechanical properties such as density and fracture energy decrease with increasing porosity, in some cases, with the appropriate porogen, remnants can stay behind in the final film and actually increase the resistance to fracture (toughness) with increasing porosity, as shown in Figure 2 . "There are many challenges still to overcome, some chemistry work that must be performed, leaving a controlled amount of remnants that do not adversely affect electrical properties, but we do believe there are possible emerging methods going forward ... to integrate these porous materials more reliably," Dauskardt said.

Dauskardt's modeling data showed that the pattern of interconnect structures has an effect on debonding and fracture resistance. "Multiscale 3-D simulation shows that it does make a difference if you propagate a debond parallel or orthogonal to a feature."

3. Etching a porous OSG material and stripping the resist results in a damaged region (right), whose size must be minimized through process optimization (left). (Source: Motorola)

Etching and ashing steps typically interact with porous low-k films and can leave a damaged sidewall (Fig. 3 ). Yu noted that it is often difficult to measure "real" film damage. "As the industry aggressively reduces feature sizes, the effects of this region on the total integrated k value will become more of an issue," she said. One example she gave was with a k=1.8 material, with no etch stop or cap layers but a k=3.0 sidewall layer at the 45 nm device node. With 70 nm lines and spaces, the sidewall region must be kept well below 100 Å wide to attain a k_eff of 2.0 or less. She emphasized the combined challenges of copper and low-k going into the 45 and 32 nm generations. "Copper resistivity is increasing as a function of grain boundary scattering and surface scattering, so to get the RC equivalent of what we are delivering today with our high-performance solutions, we have to deliver aggressive k effective values while mitigating copper resistivity issues," she said.

In terms of packaging compatibility, Yu explained that oxide-based saw processes were compatible with SiCOH dielectric, but edge chipping was observed with OSG (k<2.7) materials. During autoclave, no moisture aggression was observed.