Strained Silicon Seeing Success

Strained silicon is one of those rare new technologies that enables a fairly dramatic increase in performance with a relatively simple change in starting materials. Proof that transistors fabricated with strained silicon were faster due to increased electron mobility and velocity was first demonstrated in the mid-1980s. Then, in 1998, researchers showed it would work with leading-edge, sub-100 nm short-channel transistors. Today, companies such as Intel, IBM, Hitachi, AMD and UMC have reported success with strained silicon.

At the 2003 Symposia of VLSI Technology and Circuits, held in June in Kyoto, Japan, both AMD and UMC co-authored papers with AmberWave Systems (Salem, N.H.), a company that is licensing strained silicon technology. "At this year's sessions, people continue to show progress," noted Mayank Bulsara, AmberWave's chief technology officer. "They showed transistor performance is maintained and substantial at state-of-the-art gate lengths. For instance, AMD made transistors down to 25 nm physical gate length, which should be sufficient for 65 nm node technology. Whereas UMC focused on 130 nm node and 90 nm node technology."

Strained silicon works by growing a thin layer of silicon on top of a layer of silicon germanium. The atoms in the silicon layer align with those in the slightly larger crystalline lattice of the SiGe (germanium atoms are larger than silicon). This increase in spacing between the silicon atoms is enough to change how electrons are shared between the atoms, basically redefining how energy is shared in the conduction bands of the material. The result is increased electron mobility in NMOS devices and, to a lesser extent, increased hole mobility in PMOS devices. This leads to an increase in channel drive current and also some reductions in power consumption. "The amount of strain you apply to silicon affects holes and electrons differently," Bulsara said. "So the electrons benefit at a much greater rate than holes do. For the wafers that we consider our first-generation strained silicon technology, we are looking for 25-30% improvement in NMOS at the end of the day, and a PMOS enhancement of 5-10%."

The difference between first- and second-generation strained silicon technologies is largely the amount of germanium that's used. AmberWave has developed a process that employs a compositionally graded series of layers of SiGe, with varying germanium concentration. By gradually expanding the crystal lattice beyond that of silicon, dislocations are carefully controlled and confined to the SiGe buffer layer. Higher levels of germanium require more complicated buffer layers to reduce defects, but result in higher electron and hole mobilities.

"There is a path to get better hole mobility improvement," Bulsara said. "The trade-off there is the wafers are more challenging in terms of wafer manufacturing and transistor manufacturing. It's just not ready for implementation today; it's not that it can't be done."

One challenge is that the physics get more complicated when it comes to hole mobilities. In NMOSFETs, the SiGe is primarily a method of producing strain, where with PMOSFETs, the SiGe layer can be electrically active.

This 151-stage ring oscillator circuit was fabricated using 130 nm technology and transistors with gate lengths of 70 nm. (Source: UMC/AmberWave)

The fact that the first generation of strained silicon technology improves NMOS performance significantly more than PMOS does not appear to be a big problem. "NMOS is two times faster than PMOS anyway, in terms of bulk silicon. NMOS is always faster than PMOS. What strained silicon does is widen that gap," Bulsara said. "CMOS in general can function quite well with strained silicon and show circuit-level enhancement. The question is for types of designs people are interested in, how readily can they be adapted? That really depends on the application and there's no clear answer there."

"We are at the adoption stage where people are making prototypes. It's not just single transistors, it's the stage of making a circuit, testing the reliability and testing the performance," Bulsara said. At the VLSI conference, UMC showed a CMOS ring oscillator where the enhancement in the delay time can be translated to 17% improvement in switching speed for simple CMOS circuits. That can be traded off for 34% improvement in power savings as well, Bulsara said. The Figure shows the delay time vs. drive current of a 151-stage CMOS ring oscillator for V_cc of 0.8-1.2 V.

For additional information on emerging technologies, go to www.semiconductor.net/emerging .