Semiconductor Packaging: An Expanded Outlook
Greg Reed, Executive Editor -- Semiconductor International, 8/1/2003
The merger of Electronic Packaging & Production (EP&P) into Semiconductor International creates exciting opportunities for expanded coverage of back-end semiconductor technologies in the business press. Innovation is becoming a hallmark of the back-end technologies as they seek to emulate front-end automation, find common technical ground and generate larger proportions of total semiconductor revenue in the coming industry upturn.
To accommodate additional back-end editorial coverage, Semiconductor International has created a special demographic edition, Semiconductor Packaging, which will address all the back-end semiconductor technologies as well as the changing business models that accompany this industry segment. Each edition of Semiconductor Packaging consists of a special section inside the regular Semiconductor International issue delivered to a unique circulation in excess of 21,000 back-end subscribers.
The editorial focus for Semiconductor Packaging examines both cutting-edge and mainstream technologies. Equal coverage devoted to the materials, design, assembly and inspection/test areas define a broad spectrum of back-end technologies. Conventional packaging processes — beginning with wafer dicing, continuing through activities such as die attach, die bonding, molding/encapsulation, lead-forming/sphere attach and culminating with marking and shipping the final package — constitute central mainstream editorial topics.
On the cutting edge, innovations in packaging semiconductor devices such as ball grid arrays (BGAs), chip-scale packages (CSPs), multichip modules (MCMs) and flip-chip variations provide article topics. Additional editorial attention highlights process development, automation and tooling enhancements that impact packaging processes. As these advanced packaging technologies continue gaining market share and move toward widespread adoption, particular editorial emphasis will look at the implications of significant industry trends and drivers that enable and propel their proliferation. At the extreme edge, the latest die stacking vs. stacked package, system-in-package vs. system-on-chip, wafer-thinned die for packaging, wafer level packaging (WLP) and known good die (KGD) solutions offer ample opportunity for discourse.
Moreover, Semiconductor Packaging coverage is not limited to the print magazine. Packaging Report from Semiconductor International fulfills a similar mission in the form of an electronic newsletter. On the first and third Wednesday of each month, e-subscribers receive the latest digest of semiconductor packaging news, technical developments, new equipment and materials, and related press announcements.
On the Internet, go to www.semiconductor.net/webcasts to register for two upcoming back-end webcasts. On Aug. 21, Dieter Bergman and Jack Fisher will update the IPC's 2002/2003 National Roadmap for electronics manufacturers. Then on Oct. 1, join me and a team of technical experts in a panel discussion on wafer-level packaging drivers, assembly challenges and integration opportunities between front and back ends.
On Oct. 8 and 9, check out Reed Business Information's EOEM live Internet trade show. At the Packaging & Interconnect pavilion, view a keynote address by Chuck Bauer on microelectronic packaging; then join the discussion during complementary webcasts on stacked packages and lead-free interconnections during the technical program.
Obviously, Semiconductor International, with it's new Semiconductor Packaging edition plus ancillary electronic products, is expanding media coverage of downstream semiconductor technologies. I look forward to working with semiconductor packaging professionals in both print and electronic media. Please e-mail editorial ideas to gcreed@reedbusiness.com.
