Copper CMP Advances, Low-k Retreats

In the industry's stampede to pursue Moore's Law, planarization requirements have become increasingly demanding. This has raised concerns that, when the application of ultralow-k dielectrics becomes unavoidable, a balance between the requirement for a highly planar surface and the dielectric material's fragility may be unattainable.
 
Cost is CMP's No. 1 problem, according to Wilbert van den Hoek, chief technology officer and executive vice president of integration and advanced development at Novellus Systems (San Jose). "It's the most expensive interconnect step — probably more than even lithography. There's pressure to reduce slurries and pads costs, while curtailing slurry usage. For every milliliter of slurry used, the user pays twice: first for the slurry, then for disposal. When we do CoO calculations for deposition systems, over 75% is capital cost. With CMP, the capital cost is perhaps 25%, and the rest consumables."

"The introduction of carbon into oxides to make them low-k complicates cleaning, because it increases the water's contact angle on surfaces, making them hydrophobic," said Konstantin Smekalim, product marketing manager for metal applications at Applied Materials (Santa Clara, Calif.). "Surfaces become unreceptive to traditional post-CMP cleaning and drying solutions. This is similar to how, in an HF-treated silicon surface, water runs off in beads and drops, not as a continuous sheet that takes particles with it, but in a random manner, drying on the way and leaving residues. This requires something other than SRD for drying. The search is on for alternative drying technologies that work on either surface — hydrophobic and hydrophilic — a patterned wafer has both."

Smekalim sees copper CMP developments taking a two-pronged approach. "First, copper polishing applications at 130 nm, where volume production is ramping up, have matured, particularly those using fluorine-doped glass (FSG) as the dielectric," he said, adding that CMP is still being improved, implementing cost-cutting measures while avoiding changes that might compel it to be requalified.

"The second approach is developing polishing processes and hardware solutions that enable low-k introduction," Smekalim said. "By 'low-k' I mean a wide variety of ILD materials, including the first generation of carbon-doped oxide. Alongside come second-generation materials — carbon-doped oxide or the low-k spin-ons — requiring different polishing approaches."

Maintaining mechanical stability of the interconnect stack is a major consideration for CMP. While first-generation low-k materials can tolerate some mechanical abuse, this is not the case with the second generation of either carbon-doped oxides or spin-on low-k dielectrics. "There's a definite need to go to low-pressure CMP," Smekalim said. "Although this may seem like a logical approach, it can affect throughput. CMP is governed by the Preston Equation, which describes speed and pressure's linear effects.¹ This wasn't a concern with early attempts to polish copper over soft materials. However, when trying to make it production-worthy, questions reappear that aren't easy to resolve, because there are only a few CMP knobs to turn."

One of these is surface velocity. When increasing the pad and the wafer surface's relative velocity, results remain linear for a time. "Today's tool design permits the linear region to be extended, allowing linear velocity increases — over 1500 lft/min is attainable," Smekalim said. Rotational speeds may be high, but if the spinning object's diameter is small, sufficient linear velocity may not be attained (Fig. 1 ).

1. Ultralow-pressure (<1.0 psi) polishing is required to achieve effective, damage-free planarization on challenging features and ultralow-k films. (Source: Applied Materials)

"Material stack integrity when polishing BEOL-based low-k stacks is a concern," Smekalim said. "These materials crack and break, and stacking worsens it. Besides these materials, each with its own mechanical failure threshold, are interfaces that are no longer very cohesive. With silicon, most materials belong to the same 'family': silicon nitride, silicon oxide. Cohesiveness is excellent and delamination almost absent." Fabs must deal with the interface between various low-k materials and CVD-deposited caps. These materials have little in common, are deposited by different processes, resulting in little chemical bonding. Carbon-doped oxide is not as bad because there are two CVD-deposited materials that are chemically slightly different but not dramatically so. Still, because they are not as homogeneous as before, the interface is compromised.

Everyone is reacting differently to the low-k market's fragmentation, according to Mike Fury, vice president of R&D and engineering at EKC Technology (Hayward, Calif.). "So far, nothing has withstood the full integration and scale-up test — it's constantly back to the drawing board," he said. "On the upside, it's an encouraging environment for low-k suppliers to gamble and invest in R&D. There's a risk for all low-k suppliers, SiLK being a premier example of a considerable development investment that's still at risk."

This ripples to downstream process steps sensitive to low-k's chemical make-up. "There's a convergence to FSG, with designers using what's available instead of what's promised, carrying it to the next level rather than investing in something that may not work," Fury said. "It's a combination of technical and financial necessity. The combination of the switch to copper, low-k dielectric, and 300 mm wafer size, plus the weak economy hasn't helped."

The question is how to integrate a porous low-k dielectric. "It goes beyond mechanical weakness and compatibility issues so that the process doesn't destroy its dielectric properties — there's still the issue of how to lay a diffusion barrier on a porous surface using familiar processes," Fury said. "Even if all porous low-k problems were solved, the fundamental integration problem remains: how to keep copper from diffusing into it."

According to Adrian Kiermasz, senior director of CMP at Lam Research (Fremont, Calif.), 130 nm is in production, 90 nm is transitioning into production, and 65 and 45 nm are in R&D. "We work with all," he said. "Typically six to eight levels of metal are used, depending on where you are — 130 or 90 nm. As you planarize the metal layers in the back end, planarity, residue removal, and control become crucial. Polishing a single layer is relatively straightforward, but the complex integration issues must be understood to be successful with multilevels."

Uniformity, planarity, and defectivity control are paramount. "With uniformity control we change the pressure distribution on the wafer through the pad," Kiermasz said. "While bending the wafer may not be a problem at 130 nm, with porous films on 10 metal levels, wafer distortion might have a profound effect on device performance. A tuning mechanism that controls pad shape, passing the pressure differential to the wafer, offers better uniformity, dishing and erosion control."

Controlling down-force independently from profile tuning is important for low-k films. Because of the sensitive integration issues associated with low-k materials, precise control of the forces within a tight range is necessary. Lam has a linear design that controls removal uniformity from below the pad, integrates metrology and sensors in the head, thus enabling real-time control of removal rate profile and endpoint. The down-force comes through the membrane on the head. The linear belt design enables direct control of slurry distribution and conditioning.

"When tuning profiles, particularly with copper — a chemically assisted process — it may be necessary to tune the rate-limiting steps and, therefore, the slurry's distribution across the pad," Kiermasz said. "This provides tuning capabilities, as well as reducing waste, because the slurry is not thrown outward by centrifugal forces involved with platen rotation."

According to Novellus' van den Hoek, there are two key copper planarization challenges tied to shrinking geometries: minimizing dishing and erosion, and managing fragile low-k dielectrics. "At 90 nm or below, as copper lines get thinner, better control will demand limits to dishing and erosion," he said. "Polishing at a lower down-force, especially when reaching endpoint, will meet this requirement and also enable CMP down to fragile low-k dielectrics."

Throughput using low down-force can be managed. Different slurries enable higher removal rates; higher linear velocities also provide greater removal rates. However, offsetting removal rate loss because of low down-force by going to higher linear velocities is not viable in the case of fragile low-k materials, because the combination of low down-force and high linear velocity does not reduce the shear force that causes the soft dielectric to fail. "At 90 nm and beyond, it's evident that we'll go to a two-step bulk copper removal process using a relatively high down-force to remove 80% of the copper, and then a 'soft landing,' where the copper's last 20% is removed using a lower down-force," van den Hoek said.

In CMP, neither equipment nor technology are key, because the process is adaptable, contends Homayoun Talieh, founder and CEO of NuTool (Milpitas, Calif.). "Many have changed their roadmaps to implement ultralow-k (2.2) at the 45 nm node," he said. "They thought it'd be needed at the 90 nm node, but it didn't happen. This'll continue for at least two additional nodes. Almost everybody is going the way of Intel and using more mechanically stable CVD low-k materials at 90 and 65 nm. Porous low-k won't be adopted until 2007 or even later. CMP will continue for copper and resort to things like a lower down-force; it won't basically change any time soon."

Shumin Wang, director for copper development at Cabot Microelectronics (Aurora, Ill.), sees the industry on three generation nodes: 130, 90 and 65 nm. "Leading manufacturers have 130 nm in production. At 90 nm, technology leaders are transitioning from R&D into pilot line mode. Current R&D activities are primarily focused on 65 nm development; however, these are at an early stage, particularly since final low-k film selection, and the integration scheme, are incomplete."

The industry roadmap has delayed the 65 nm introduction of ultralow-k dielectrics. This resulted from complications with the multiple low-k films and cap materials, and novel integration schemes. "As a consumable supplier, we see the challenges in the multiple choices of low-k films and variety in integration schemes," Wang said. "Consumables must be designed flexibly to meet those varying needs. The manufacturer must determine what's involved in deposition of different kinds of materials, robustness of low-k films, and how well they adhere to adjacent layers like the barrier and caps. Mechanical damage tolerances are reduced due to thinner lines, softer dielectrics, and higher metal densities." Defectivity control is another concern. Defectivity goes beyond just scratches or physical damage. New materials bring a new set of defects.

Motorola's MOS-13 wafer fab (Austin, Texas) is running high-volume 130 nm CMOS with a conventional dielectric back-end process, according to Jeff Cadenhead, copper CMP process engineer at the fab. "We've run our process in production for two years — one year at high volume. We're in development mode for our 90 nm process with low-k."

A key point in Motorola's copper fab has been slurry development implementation in conjunction with DuPont Air Products NanoMaterials (Carlsbad, Calif.). "It enabled us to run the 130 nm process, and improved our ability to hit sheet resistance targets without leakage window sacrifice," Cadenhead said. "This made the process electrically robust, freeing us to deal with manufacturing issues such as cost and scrap, resulting from tool problems, integration questions, etc. We back-qualified the slurry on older copper technologies (180 nm), also improving that process. For copper processes in our fab — from 180 nm to development work on 90 nm — we only run that slurry."

The biggest problem in fine-tuning the slurry was defectivity control — environmental issues. Initial production was not done in a high-volume facility designed for slurry manufacturing, and there were biological issues, with bacterial and fungal growth in the slurry. "The biggest issue was controlling the slurry's quality from one batch to the next, and avoiding biological issues," Cadenhead said. "Now, we haven't had to make formulation and makeup adjustments in two years."

It is critical to partner with the IDM, according to Todd Buley, semiconductor integration engineer at Rodel (Phoenix). "Our customers work with different integration architectures. We're developing 'tunable' slurry families. Before, you could have only one slurry. Now, you're so affected by the toolset, pads, etc., that you must 'tune in' the exact architecture. It's worse with ultralow-k, because you're working with multiple films." (Fig. 2 )

2. Because different IDMs work with different integration architectures, different types of slurries are needed. A close partnership between the consumables provider and the device manufacturer is needed to enable the proper “tuning” of consumables, particularly when working with ultralow-k materials. (Source: Rodel)

What once was termed a "selective slurry" is meaningless now, added John Quanci, copper slurry R&D manager at Rodel (Newark, Del.). "It isn't uncommon to have a copper layer, then a barrier layer, and for the barrier to be Ta, TaN, and then underneath one or two capping layers. Some want to remove the cap, thin it, stop on the first cap, stop on the second one, stop on the ILD. The permutations are considerable, so we laid out the main integration architectures and came up with a base set of two or three slurries — a mix of selective and non-selective — and tune individual films off of them. The customer takes two or three base slurries, runs them through and picks the one that works best. Then we take those numbers and plug them into semi-empirical models — a mixture of data and fundamental reaction kinetics — and we can quickly tune it."

Rodel is trying to develop slurry/pad combinations that reduce stress while maintaining high polish rates to avoid delamination. "The process is of a chicken-or-egg nature, and as the industry matures around low-k materials, it'll be solved," Buley said. "Meanwhile, we must prove that we can polish these materials without delamination. The industry should default to a few proven integration schemes."

Unless a stable material becomes available, the shift to porous low-k will not happen soon. There are integration, contamination and delamination issues that will worsen with multilevel architectures. As Buley put it, "We must stop acting as if copper were aluminum."

A migration to k<2.5 porous low-k materials within the next five years is unlikely. A battle is pending between the technology and design worlds. Technology can produce the device but not package it. Design demands performance improvements, and lower-k. With truly porous low-k the solution is to go to CMP processes that give 0.5 psi down-force, but throughput cannot be propped up with higher linear velocities because of shear.

If the industry goes to low-k and retains conventional CMP, throughput must be reconsidered. The direction can be twofold: planar plating, a process that eliminates the overburden, followed by a short, low down-force CMP process to remove the remaining 2000 Å of overburden, then the barrier, and stop. Lower throughputs then become acceptable, because instead of removing 1 µm, 2000 Å are removed maintaining the same 40 wph. If planar plating is unresolved, electropolish may be used to electrochemically polish off the bulk of the copper, create a wafer with a planarized 2000 Å copper overburden, and then use CMP to remove it in low down-force mode.

The endgame is nowhere in sight, because we do not know all the rules yet.