Trench Etch Optimization with 193 nm Resist

Copper and low-k dielectrics have been introduced into semiconductor fabrication at the 0.13 µm node to lower the circuit RC time constant, thereby increasing device speed.^1,2 The use of low-k dielectrics in back-end-of-line (BEOL) integration has posed great challenges in the etching process.³ For example, a smaller process window is expected for low-k materials based on organosilicate glass (OSG) because of its lower etch stop selectivity. At the 90 nm node, an additional challenge is faced as 193 nm lithography is used at critical levels.

Introduction of 193 nm lithography has improved lithographic capability. However, it has also created significant integration challenges for pattern transfer.⁴ Compared with 248 nm resists, 193 nm resists are generally not as mature, and have inferior etch resistance and reduced mechanical stability of printed features. Furthermore, thinner 193 nm resists are generally used in comparison to 248 nm resists. Some novel integration schemes such as metal hard masks, multilayer resists, new etch chemistries, and pre-etch treatments have been proposed to solve the issue.⁴

We will first present various issues faced in trench etch of 193 nm resist in 90 nm copper/low-k integration and approaches taken to resolve them. Similar phenomena have been reported from the etch perspective.⁴ In addition, electrical performance of the unit process developed will be highlighted. We found that, despite all the challenges of 193 nm resists, an excellent etch process with good electrical response and yield from large-area test structures can be achieved primarily by tuning the etch process.

Copper/PECVD OSG technology has been adopted for the metal trench local-layer interconnects. The metal trench dielectric stack consists of a 500 Å etch stop layer, 2000 Å OSG and 2000 Å SiO₂ hard mask. The designed wire pitch is 240 nm (120 nm trench/120 nm space). The thickness of organic BARC and 193 nm resist on top of the oxide hard mask are 700 and 3340 Å, respectively. After trench formation and copper plating, copper CMP was done with an abrasive-free process, which leaves behind a ~700 Å hard mask on top of the OSG. Electrical test was then performed to evaluate the performance of the metal trench local-layer interconnects.

The metal trench etch consists of five steps: BARC opening, hard mask etch, OSG etch, resist stripping and bottom etch stop layer breakthrough. Good selectivity between BARC and hard mask can en-sure sufficient resist margin for hard mask and OSG etch as no excessive over etch will be required during BARC opening. We aimed to obtain an acceptable pattern transfer after etch for integration.

There are a few key issues related to 193 nm resists:

1. Cross-sectional and tilt views show severe line bending or weaving after OSG trench etch (top); and elimination of line bending or weaving with the optimized etch process after resist strip (bottom).

2. Degradation of 193 nm resist surface after etch.

Line bending: Figure 1 (top) shows line bending or weaving problems associated with 193 nm resists. In particular, resist lines tend to fall over during etch, sometimes with a quasi-periodic, alternating pattern.⁴ This can create twisted or weaving lines and spaces in the dielectric film, or regions of incomplete etch where the dielectric becomes shaded. Note that this phenomenon only occurs at areas with a dense trench pattern. Through a detailed partition study on the effect of different etch steps, we found that, by lowering the plasma power and argon flow for the hard mask etch step, line bending could be totally eliminated (Fig. 1, bottom).

Resist surface degradation: The most difficult challenge with 193 nm resist is associated with its surface integrity upon exposure to plasma, and this could hamper the integration effort. Figure 2 shows the deformed or rough surface of 193 nm resist after etch. In contrast, this recipe has little impact on 248 nm resists. Surface or mask degradation causes the resist thickness on its surface to vary widely. During etch, thinner regions may etch away faster, thus increasing the roughness and creating deep pits in the resist.⁴ Accumulation of charges around the peaks of resist may explain the enhanced etch rate in the valley regions, which further aggravates the surface roughness. In extreme cases, if the resist is completely removed in these regions, the underlying dielectric will be rapidly etched. This will cause pinholes on top of the hard mask and striations at the dielectric sidewall (Fig. 3 ).

3. Top and tilt SEM images of post-etch wafer showing surface pitting and sidewall striation.

Surface pitting and sidewall striations: Surface pitting and sidewall striations are results of resist surface degradation after etch. They appear as pits on top of the hard mask and vertical grooves on the sides of trench lines (Fig. 3 ). They may be initiated by pre-existing or evolving irregularities in the resist, which are transferred to the underlying dielectric film during etch.⁴ Line edge roughness manifested by sidewall striations will undermine in-line CD monitoring and accuracy of the measurement. In addition, striations in the dielectric reduce the space-to-line ratio and can create shorts between copper lines (Fig. 4a). Figure 4b shows a TEM micrograph of metal lines after copper fill and CMP. The copper protrusions observed on the sidewall are the result of sidewall striation after etch. These metal lines are very prone to electrical shorts as the effective space between two lines has been significantly reduced.

4. Impact of sidewall striations after copper CMP. Observation of copper line edge roughness after CMP from surface SEM (a) and copper sidewall protrusion from cross-sectional TEM (b).

To eliminate both surface pitting and sidewall striations, we have to first minimize resist surface degradation. Through etch partition studies, we found that both hard mask and OSG etch steps contribute to resist surface degradation, which in turn cause surface pitting and sidewall striations. By changing the hard mask etch chemistry from CF₂H₂/Ar/O₂ to CF₄/C₄F₈/O₂, we managed to suppress surface pitting and sidewall striations significantly. Besides lowering the rf power, the etch chemistry was changed from CF₂H₂/Ar/N₂ to C₄H₈/Ar/N₂ for OSG etch to ensure sufficient top and sidewall polymer protection to eliminate surface pitting and sidewall striations. In short, we chose a more polymerizing chemistry and reduced rf power to eliminate the issue.

5. Optimized etch process showing reasonably good profile and defect-free surface at wafer center (left) and wafer edge (right).

Figure 5 shows the desired post-etch profile and defect-free surface using the optimized etch process. Figure 6 shows the copper lines after copper filling and CMP from both surface SEM and cross-sectional TEM. They are totally free of line edge roughness and sidewall protrusion compared with Figure 4 .

6. Surface SEM and cross-sectional TEM showing post-CMP copper lines with optimized etch process.

Figure 7 shows the full map electrical leakage results of a comb structure and continuity results of a Meander structure. Both structures are about 11 m long. The drawn linewidth and space are 0.12/0.12 µm. The comb leakage was measured by applying 4 V across the structure. Process A refers to an etch process that has surface pitting and sidewall striations issue and the comb leakage yield is only 25%. Occurrence of hard shorts for Process A is also confirmed from the low resistance tail in the Meander resistance plot.

7. Comb leakage (left) and Meander resistance (right) results for three different etch processes.

By optimizing the hard mask etch, which is known to contribute the most to the 193 nm resist's damage, the comb leakage yield improved significantly to about 90% (Process B). On the other hand, 98% comb leakage yield has been achieved for Process C, which was obtained by further tuning all the etch steps, particularly the OSG etch.

Figure 8 shows the voltage-ramp test results for large-area metal combs with a line/space design rule of 0.12/0.12 µm for Process A and C, respectively. The purpose of the voltage-ramp test was to further confirm the robustness of the process, so only those sites without initial leakage failure were tested. The results showed all metal combs etched using Process A suffered premature dielectric breakdown, while those etched with Process C remained stable under an electrical field up to 30 V or ~3.0 MV/cm. Due to formation of sidewall protrusions (Fig. 4 ), the effective space between two copper lines has been reduced such that hard short can occur at relatively low electrical field. This observation confirms that Process C is free of sidewall striation issue. Our preliminary reliability investigation has also confirmed that the line edge roughness has an adverse impact on biased thermal stressing (BTS) failure.

8. Voltage ramp responses of a wafer etched with Process A (left) and Process C (right).

Introduction of 193 nm resists with properties inferior to those of 248 nm resists has posed many challenges to etch processes. Line bending, resist surface roughening, and surface pitting and sidewall striations are the issues encountered with 193 nm resist etch. We have discussed the various steps taken to solve these issues from the etch point of view. We have also discussed their corresponding electrical response upon integration. We show that these issues can be overcome through optimizing the etch recipe without resorting to complicated changes such as using as metal hard masks, multilayer resists and pre-etch treatments.