E-Beam Inspection Goes In-line

Things keep changing in the semiconductor industry — not only in the technology but also in its application. In the recent past, e-beam inspection tools were primarily used during process development and early yield ramping. Once production levels were reached, the process was pretty well locked in and there was little requirement for in-line inspection using tools beyond optical tools in widespread use.

This situation has changed, largely due to a preponderance of sub-surface defects, in logic and memory technologies, which persist in production. These recurring defects are difficult to eradicate fully during development because of extremely tight process windows, which leads to costly yield excursions in production. Though optical inspection is faster, many of these defects are best detected by electrical means due to the correlation between electrical defectivity and yield loss. "Almost 90% of all electrical defects are yield killers," said Raj Persaud, senior director of marketing for the E-Beam Inspection Division at KLA-Tencor (San Jose).

In the interconnects of logic devices, the most common defects are copper voids, which form for a variety of reasons, including discontinuous barrier film. In memory cells, contact under-etch is a leading cause of voids in high-aspect-ratio capacitors (>15:1). "The No. 1 line monitoring step for logic device manufacturers is copper CMP, followed by via 1, and then contact," Persaud said.

One memory manufacturer estimated that a single yield excursion caused by contact under-etch cost the company >$13M/event. Texas Instruments (Dallas) determined that via contamination, which appeared as a dark voltage contrast defect after M2 CMP, was causing copper voids. In-line e-beam monitoring enabled a 15-20% improvement in yield (see "Electrical Line Monitoring in a 300 mm Copper Fab").

KLA-Tencor recently introduced an in-line e-beam inspection tool, the eS30, which builds on the success of its predecessor, the eS20XP, but offers drastically increased inspection speed. For instance, the typical inspection time (including overhead) of a single 200 mm wafer on the eS20XP system is 53 min vs. 18 min on the eS30. "E-beam inspection is slower than optical, so you need an ROI that justifies putting it in production," Persaud said.

The company estimates that, of the 35 copper fabs that have e-beam inspection tools, about 14 are used in-line. By increasing the speed of e-beam inspection, engineers can find defects in-line and fix the problem quickly, while minimizing process tool downtime and product at risk.

In developing the tool, the goal was to have a system capable of inspecting features for the 65 nm node (requiring smaller pixel size and higher resolution), while maintaining acceptable throughput for in-line monitoring of 90, 130 and 180 nm processes. However, the higher the sensitivity, the greater the volume of defects detected, which drives the need to more quickly separate yield-relevant defects from nuisance defects.

The eS30 system treats the inspection data faster while also scanning faster. Scan speed was increased by making the electron column shorter, increasing the electron density and reducing signal noise. Die mapping is accomplished using a laser and sensors for dynamic feedback of the wafer location. The improvements in signal-to-noise ratio allow a faster scan. "Before, on some layers, we had to scan the same area five to six times to get enough signal," Persaud said. "Now that same analysis can be done in one scan."

The sensitivity on optical tools is usually improved by raising the photon density and/or decreasing the wavelength. In the case of e-beam tools, sensitivity is a function of electron density and landing energy. The eS30 system features a smaller minimum pixel size — the diameter that the collimated beam of electrons is restricted to —as well as a wider range of landing energies. In some instances, a 0.1 µm pixel can be used to detect 65 nm defects. The larger the spot size, the more quickly the entire wafer can be scanned. A new charge-controlling mechanism also improves scan speed by enabling the use of a larger spot/pixel size.

The eS30 is in beta testing at two of the top five semiconductor manufacturers. At KLA-Tencor's recent Yield Management Seminar held during SEMICON Japan, Toshiba discussed the ability to use voltage contrast e-beam inspection with in-line automatic defect classification to identify and eradicate voltage contrast defects at copper CMP and tungsten plug CMP. Using a pixel size of 0.3 µm and sampling 8% of the area/die over the whole 200 mm wafer, inspection time was reduced to 50 min/wafer on the eS20 tool.

Of course, cutting cost is a primary driver in the industry. A leading DRAM manufacturer estimates that a single eS30 tool used for self-aligned contact inspection paid for itself in less than six months. The same manufacturer determined that, by implementing electrical line monitoring for a 200 mm fab with 20,000 wafer starts/month and with a processing cost of ~$1000/wafer, a reduction of the time to excursion detection from 30 days to one day results in a $20M savings. KLA-Tencor estimates that the eS30 tool offers up to a 6× improvement in cost of ownership over the first eS20 tools.

For additional information on yield management, go to www.semiconductor.net/yield.