Nanoscale Diffusion Barriers for Copper Metallization

The most commonly used barrier materials are tantalum and TaN. Compared with copper, these are highly resistive metals, which will increase the effective resistance of an interconnect. For an assessment of barrier scaling, two different cases have to be considered (Fig. 1 ). In the first case, the copper line, the barrier is connected in parallel to the copper conductor. The barrier should be kept as thin as possible to leave as much cross-sectional area as possible for the copper. The resistivity of the barrier is not of much concern here. In the second case, the via, the electrical current has to cross the barrier layer to pass from one metal layer to the other. To keep the via resistance to a minimum, the product of barrier resistivity and barrier thickness must be minimized.

1. Schematic drawing of a via connecting copper lines in two different metallization layers.

As the barrier thickness is decreased, it must be verified that the layers still work as effective diffusion barriers. The best place to investigate the functionality of the layers is the place where they come into operation: in the damascene structure. The functionality can be tested by applying an electric field between adjacent lines and measuring the leakage current, since the degradation of the oxide by copper diffusion would result in an increase of the leakage current. Copper diffusion was further enhanced by annealing the samples or by applying a bias voltage at elevated temperatures (bias temperature stress, BTS).

Adjacent copper lines represent the electrodes of a capacitor. The total length of the capacitor test patterns used was 2.1 m for a structure having a footprint of only 4 mm². For metallized damascene trenches with large linewidths (~500 nm), the barrier layer thickness at the bottom of the trench is approximately the same as the nominal barrier layer thickness (Fig. 2 ). On the sidewalls of the structures, however, the thickness of the barrier layer is much thinner than the nominal thickness (in our experiments typically 30% of the film thicknesses obtained on blanket dummy wafers). Thus, for a barrier with nominal 2 nm TaN/10 nm Ta, the effective barrier thickness on the sidewalls did not exceed 4 nm.

2. TEM micrograph of a metallized damascene trench. The nominal barrier thickness was 2 nm TaN + 10 nm Ta. The actual barrier layer thicknesses at the bottom and at the sidewalls are 12 nm and 3-4 nm, respectively.

In the first case, the structures have been annealed at 450°C for 48 hr. Afterwards, the leakage current density vs. the electric field was measured between adjacent lines (Fig. 3). Several test structures with nominal barrier layer thicknesses from 10 nm TaN/40 nm Ta (used in a current product and therefore serving as a reference) down to 5 nm Ta have been investigated. These thicknesses correspond to effective barrier layer thicknesses ranging from 17 nm down to less than 2 nm. At low electric fields (≤3 MV/cm), the leakage current is extremely low and the bias has only little effect on the current density. At higher electric fields, the leakage current increases further, but structures with different barrier layers do not show any significant difference. This also holds true for the profile shown in Figure 2 , which was investigated as a worst-case situation because of the re-entrant angle of the profile.

3. Leakage current density vs. applied electric field strength. The current densities between adjacent trenches are shown for different barrier layers. For comparison, the worst case for operational stress of ~0.41 MV/cm is indicated, which is expected for low-standby-power circuits in the 22 nm node (note that 5 nm blanket tantalum means 1.7 nm on sidewalls).

For BTS, a constant electric field (0.75-1.8 MV/cm) was applied between neighboring lines at elevated temperature (T=200°C). After certain time intervals the leakage current level of the test structures was checked at room temperature. In addition, the leakage current level of a similar set of unstressed structures was checked as a reference. The stressing in these experiments was much higher than the worst-case assumptions (~0.41 MV/cm, Fig. 3 ) described by the ITRS for operational stress in 22 nm node low-standby-power products.¹ Even after 2000 hours of BTS, no significant change of leakage currents was seen for all barrier and barrier bilayers investigated.

According to ITRS requirements, the specific via resistance must decrease from about 0.1 Ω/µm² to <0.01 Ω/µm² when going from today's 100 nm products to 22 nm node products in 2016. The main part is caused by the barrier layer at the via bottom. Therefore, it is important to investigate the resistivity properties of the barrier material and to estimate the influence of barrier layer in the via.

Tantalum films deposited on SiO₂ show a resistivity of about two orders magnitude higher than copper (ρ_Cu~1.9 µΩ-cm). TaN exhibits an even higher value (ρ_TaN~235 µΩ-cm). However, when depositing a stack of TaN/Ta on SiO₂, the resulting layer exhibits a much smaller resistivity — only one order of magnitude higher than copper.

The explanation of this strange behavior is that tantalum can grow in two different crystal structures² with substantially different electrical resistivities (Fig. 4 ), in the body centered cubic crystal structure (α-Ta), and in the tetragonal crystal structure (β-Ta). The ratio between the resistivities of these two phases is nearly 10. Bulk tantalum usually crystallizes in the α phase (ρ~20 µΩ-cm). However, when tantalum is deposited on a SiO₂ layer, it grows in the highly resistive β phase. Introducing a layer of the highly resistive TaN between the SiO₂ and the tantalum layer, tantalum is forced to grow in the desired low-resistivity a phase. To minimize the resistivity of the entire stack, the thickness of the high-resistivity TaN layer should be reduced as much as possible, without losing the low-resistivity a phase of tantalum.

4. The crystal structures of tantalum with their respective resistivities. Deposition of tantalum on SiO2 yields the highly resistive β phase, whereas tantalum deposited on TaN shows the low-resistivity α phase.

TaN layers of different thicknesses were sputtered on the SiO₂ surface of blanket wafers. Then tantalum layers of 50 nm thickness were deposited on TaN. At a TaN thickness of 8 nm, the resistivity is ~32 µΩ-cm, indicating the a phase of tantalum (Fig. 5 ). With decreasing thickness of TaN, the resistivity of the complete stack decreases slightly. This can be attributed to the fact that the contribution of the TaN layer to the total barrier stack decreases. At a TaN thickness of ~0.7 nm, the resistivity shows a minimum. At thinner layer thicknesses of TaN, the resistivity suddenly increases to the value of the highly resistive β-Ta phase. In this regime, a highly non-uniform resistivity distribution is observable on the wafer, which is probably an implication of the very short processing time.

5. Dependence of the TaN/Ta barrier resistance on the TaN layer thickness. The thickness of the tantalum film was kept constant (50 nm).

The resistivity of the TaN layer is strongly dependent on its nitrogen content, which can be adjusted by the N₂ flow rate during sputtering. For further reduction of the barrier resistance, it is important to determine the amount of nitrogen that is needed to grow the desired low-resistivity phase of tantalum. For a series of wafers, the N₂ flow rate was changed, resulting in TaN layers with different nitrogen contents. The resistivity decreases slightly with decreasing N₂ flow (Fig. 6 ) because nitrogen-deficient TaN shows a higher conductivity. At a flow rate of about 7 sccm, the resistivity shows a minimum. At lower flow rates, the resistivity increases to much higher values, indicating the transition from the low-resistivity α phase to the high-resistivity β phase.

6. Dependence of the TaN/Ta barrier resistance on the N2 flow rate during TaN deposition. The layer thicknesses are kept constant for TaN (10 nm) and for tantalum (40 nm).

Based on these results, the via resistances have been calculated and compared with roadmap requirements (Fig. 7 ). Four different barrier configurations with varying total barrier layer thickness have been considered. In the case of TaN/Ta bilayers, a 1 nm thin TaN layer was assumed to be sufficient to allow deposition of tantalum in the low-resistivity phase.

7. Specific via resistivity for different barriers (α-Ta, 1 nm TaN + Ta, β-Ta, TaN) depending on the layer thickness. For comparison, ITRS requirements are also shown.

For the calculation of the via resistances, the aspect ratios suggested by the ITRS were used and the increase of copper resistivity for shrinking dimensions due to size effects³ was also taken into account, whereas any contact resistances between the layers were not included. The estimation shows that the resistance curves of vias including barrier layers with α-Ta and 1 nm TaN + Ta are distinctly below the resistance values of the roadmap. Only in the case of vias with β-Ta or TaN barriers the via resistance may possibly intersect the resistance curve of the roadmap.

The decreasing specific via resistance may lead to the inaccurate assumption that the via resistance is decreasing also. But the resistance per via behaves in a different way. As the cross-sectional area of a via decreases with the square of the feature size, the resistance per via is significantly increased by downscaling as depicted for two barrier films (Fig. 8 ).

8. Resistances per via using TaN and α-Ta barriers depending on the node size.

The functionality as well as the electrical properties of thin tantalum-based barrier layers were examined. Leakage current measurements of annealed structures for effective barrier layer thicknesses down to sub-2 nm thicknesses show no significant change. The influence of the TaN layer on the resistivity of the TaN/Ta barrier bilayers was investigated. Even for TaN layer thicknesses as low as ~0.7 nm, the succeeding tantalum layer still grows in the low-resistivity a phase. By reducing the nitrogen content of the TaN layer, the resistivity of the barrier stack could be successfully decreased further.

Calculated resistances of vias with an optimized TaN/Ta barrier layer meets the ITRS requirements until the end of the roadmap. Overall, no roadblocks for the realization of vias with resistances complying with end-of-roadmap requirements were found. This would extend the applicability of the current barrier concept far beyond the scope of the current roadmap. The barrier films were all deposited by PVD, indicating the potential for an extendibility of this deposition technique for future technology nodes.