3-D ICs: How They Stack Up at RPI

As IC makers try to pack more functionality on a chip, they are running into several problems. Die sizes get larger, and therefore more sensitive to "killer" defects caused by the stray bit of dust or contaminant. Interconnects across the die are also longer, leading to longer time delays. And it can be difficult to integrate several different types of devices (i.e., logic and memory) onto a single chip without resorting to complex processing schemes.

These are just some of the challenges of today's system-on-a-chip (SoC) integration. But what if it weren't necessary to integrate many different functions on the same chip, but build them separately with high yields, and stack them together to create a reliable 3-D IC? That's the goal of associate research professor "James" Jian-Qiang Lu and fellow researchers at the Focus Center-New York, Rensselaer: Interconnections for Gigascale Integration at the Rensselaer Polytechnic Institute (RPI, Troy, N.Y.). Lu believes that a strategy where several wafers are bonded together and interconnected provides a more effective means of integrating chip technologies, while also increasing performance.

"We're developing monolithic wafer-level 3-D integration processes that potentially can achieve all the advantages of system-on-a-chip and system-in-a-package, while lowering cost, enabling the use of small form factors and achieving high performance," Lu said. At last month's International Interconnect Technology Conference (IITC), Lu presented recent work with co-authors from RPI and International SEMATECH (Austin, Texas).

Cu/oxide interconnect structures after bonding to a glass wafer and Si substrate removal by grinding, polishing and TMAH etching. (Source: Rensselaer Polytechnic Institute)

Lu explained how the process works: "If you have three wafers, you finish almost all the processing on each wafer," he said. "Then you align two of them and bond them together, face to face. Then you thin the backside of the top silicon. This is followed by inter-wafer interconnect, a process that we call drill, fill and mill, to connect the wafers. This means you drill a hole using dry etching, then fill it with metal, such as copper, and do CMP (i.e., copper damascene patterning). Once you complete these two wafers, you can repeat the process for the third wafer: aligning, bonding, thinning and inter-wafer interconnection."

Critics of this approach point out that a wafer with 80% yield bonded to another wafer with 80% yield could result in a product with 64% yield. Lu, however, argues that, for a given set of system specifications in terms of performance and funtionality, with his approach, yield would be greatly improved because of the smaller die size and because the processing of each wafer can be simpler and optimized. "Because you can separate different processes on different wafers, you can use mature technologies, which can increase the yield," he said. "The die size is smaller, which also increases the yield. Finally, because you use a small die size with short vertical inter-wafer vias to replace the long-distance interconnects in large die in 2-D integration, your interconnect delay is low, so you may not have to use a high-risk (interconnect) technology."

Of the four key processes required for 3-D wafer-level integration — wafer alignment, bonding, thinning and inter-wafer interconnection — bonding and thinning are of the greatest concern in establishing a viable process flow that is compatible with the BEOL process, according to Lu. Alignment is done at room temperature, and the interconnection process is similar to BEOL interconnect processing. But bonding and thinning involves potentially harmful mechanical and thermal processes, such as mechanical grinding.

Lu's work presented at IITC investigated the impact of wafer bonding and thinning processes on the performance and yield of wafers. Wafers with state-of-the-art two-level back-end copper interconnect test structures with two types of interlevel dielectrics (ILDs) were evaluated. Various procedures were developed for specific evaluation purposes, including visual inspection using thermal coefficient of expansion (TCE) matched glass wafers; mechanical bonding strength tests using four-point bending/delamination techniques; and electrical tests of the processed wafers. Wafer bonding and thinning processes with the 3-D approach can preserve the mechanical integrity of the interconnect test structures with oxide or porous low-k ILDs, although the bonding and thinning process is marginal and needs improvement with porous low-k ILDs.

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