Stacked CSPs: Issues and Results

System requirements for high-density packaging have driven the development of chip-scale package (CSP) technology. Continuing pressure for improved performance and reduced cost is dictating even greater improvements in functional density. A prime example of this can be found in the escalating requirements for DRAM and other memory modules.
 
Functional integration within the silicon and bare chip stacking are two approaches to these challenges, but they present problems related to cost, time-to-market, testing and business logistics. Stacking tested CSPs — rather than bare chips — addresses each of these issues because of increased design flexibility, the ability to extend the life of existing products, an established manufacturing infrastructure, and elimination of the technical and business challenges of testing bare die.

With proper design, CSP stacking is a straightforward extension of standard packaging and surface-mount processes. This article reviews the manufacturing flow for one such stacked CSP technology, the µZ-Ball Stack. The electrical and thermal performance of the resulting structures is also evaluated.

The benefits of chip-scale packaging have been known for many years. The ability to house a chip in a package that is essentially the same size as the chip itself provides many advantages in terms of system integration, performance and cost (even if the package itself carries a cost premium, it typically results in system-level savings because of smaller boards and other related cost reductions).

A natural next step to extend the advantages of CSPs is to put more than one chip inside a package. This might be especially appealing with the emergence of advanced wafer thinning capabilities. However, stacking of bare chips presents significant challenges other than the package itself even when the packaging technology is in place that allows multiple chips to fit within a single-chip, Z-axis constraint.

When packages are stacked instead of chips, it is possible to test the devices before stacking, thus avoiding the challenges of testing bare die. Although there have been advances in the technology of wafer-level burn-in and test, the options for cost-effective processes and equipment are limited. An alternative is to allow a final product yield that is the product of the yield of each component in the stack, but the rapid decline in overall yield as the number of chips increases makes this unappealing for all but the highest-yielding devices.

1. Stacked CSPs can be used in DRAM modules and other applications requiring high density in the X-Y-Z directions.

Stacking CSPs also allows more flexibility as the chip design evolves, with die shrinks for example. With a revision to the chip design, a straightforward redesign of the CSP substrate retains the same CSP footprint on the board. With bare chip stacking, a new die size and set of pad locations might require an extensive redesign of the system to accommodate the changes. A typical application of stacked CSPs is in DRAM modules (Fig. 1 ), and this is an application where it is especially important to maintain a constant footprint even as die generations change quickly.

A stacked approach

The µZ-Ball Stack package is a CSP-stacking approach that leverages existing µBGA technology. Figure 2 shows the structure of a four-die stack with center-bond DRAM chips. Each layer of the package is essentially a µBGA (Fig. 3 ). The structure includes a compliant layer that significantly increases the reliability of the package.

2. A cross-section of a four-die µZ-Ball Stack package. The total height is 2.28 mm with a die thickness of 0.15 mm (the thickness of the two-die stack is 1.29 mm).

3. The µZ-Ball Stack leverages the high-reliability structures of the µBGA.

Some design and manufacturing issues are created by the need to stack the chips. For example, to stack multiple chips, it is necessary for the substrate to extend beyond the edge of the chip. As shown in Figure 2 , however, this configuration adds a relatively small amount to the total area of the package, especially for relatively low-pin-count devices such as DRAMs.

A 'chip select' process

It is also necessary to have a process that differentiates the chips in the stack so that it is possible to identify the active chip at any given time while the stack is functioning. This "chip select" process can be accomplished in two basic ways. The first is to have multiple bond pads on the substrate, then to wire bond from the chip to the bond pad that corresponds to its position in the stack. This approach makes each layer unique at the wire bonding step, which is technically straightforward but creates inventory issues because it increases the number of visually similar but functionally distinct parts in the product.

The other chip-select technique keeps each layer identical through the manufacturing flow until the stacking process. This involves creating on each substrate an open in the circuit trace that corresponds to each position in the stack except for the one actual position of the chip in the stack. This can be accomplished with a punch or a laser, for example. This adds a step to the process flow, but it simplifies the inventory and increases flexibility in the final assembly.

The stacking process is the only major process that is not part of the standard µBGA manufacturing flow. It is, however, entirely compatible with standard surface-mount technology. The stacking process consists of:

• Flux preparation: Flux material is spread manually or with a rotary flux station to a controlled thickness of 20-30% of the solder ball height.
• Package flux dip: The package is applied to and removed from the flux area (using conventional pick-and-place equipment), with the flux adhering to the solder balls.
• Package stacking: The base unit and pre-fluxed units are stacked using conventional pick-and-place equipment.
• Reflow: Stacks are loaded in a fixture and run through a convection reflow furnace.
• Finish: Clean, inspect, test, pack, ship.

The µZ-Ball Stack package has been through design iterations to meet the same reliability levels as the baseline µBGA technology. In particular, an early design of the stacked CSP saw some early failures in thermal shock, with the solder balls separating from the substrate.

To solve this, the solder mask opening and solder ball diameter were increased to improve the overall structure strength. The resulting reliability performance includes a four-die design with PbSn eutectic solder balls passing the following tests:

• Board-level thermal shock (-40/+125°C, level 2 preconditioning), 1000 cycles.
• Autoclave (121°C, 100% RH, 2 atm, 168 hr).
• Moisture sensitivity level 2.
• Drop test (five drops each axis, 1500 G acceleration).

4. The finite element method can be used to calculate the inductance and resistance of stacked CSPs (a boundary element model is recommended for capacitance calculations).

Electrical simulations have been used to demonstrate the benefits of CSPs and the relative performance of the µZ-Ball Stack package. For example, the model shown in Figure 4 was used to calculate inductance and resistance values of a two-high stack of 512 Mb DDR SDRAM devices (die size = 7.14 × 19.77 mm, package size = 11.8 × 20.4 mm, center bond pads).

The typical self-inductance was 4.5 nH, compared with 7 nH for a typical stacked fine-pitch BGA, or 10 nH for a stacked TSOP. The inductance scales closely with the length of the interconnect, so much of the benefit of stacked CSPs results from the short traces compared with other stacked packages that require interposers or large fan-outs. The average capacitance was 0.86 pF, which is noticeably more than for a single µBGA (0.2 - 0.3 pF), largely because of the traces needing to travel approximately half the width of the die to reach the solder balls just beyond the edge of the die. This is the case for any stacked package because of the need to route around the chips to the PCB to which the package is mounted. Again, the CSP format minimizes that effect by requiring very little interconnect beyond the edge of the die.

Thermal simulations also have been performed to understand heat transfer characteristics of the package. For this analysis, a die size of 6.67 × 14.38 mm and package size of 10.6 × 15.4 mm were used, and the structure was a two-high stack mounted on a four-layer JEDEC-style test board.

An interesting result was that the temperature in each chip was nearly independent of the source of the power, i.e., whether all of the heat was being generated in the bottom chip or the top chip (Table ). This allows a meaningful θja to be defined for the package as a whole, rather than needing to differentiate among the chips in the stack. For this package, θja = 22°C/W in still air, and modest air flow (1 m/sec) reduces that value to 11°C/W.

Conclusions

Stacking CSPs instead of bare chips has been identified as an appealing solution for the challenges of integrating multiple chips in small form factors. One such approach, the µZ-Ball Stack package, has been developed and demonstrated.

Volume manufacturing issues have been solved, and the electrical, thermal and reliability performance of the package has been evaluated in detail. The size of the package and sound design features result in good electrical performance. The short thermal paths allow good heat transfer and the compliant µBGA structure results in excellent reliability.