SEMICON West 2003 Exhibitor Outlook comments

Advance Energy Industries Inc.
Craig Jeffries
Executive Vice President, Chief Marketing Officer

China's entry into the WTO signaled an important transition — and opportunity — for the worldwide semiconductor industry. To survive and prosper, companies are responding with increased commitment to the enormous growth, demand and opportunity China presents.

Many top companies have maintained a sales-and-service presence in China for years. For example, AE established a presence in China in 1997, and now has an office in Shanghai. Because the Chinese government actively encourages semiconductor manufacturing in the Changjiang Delta around Shanghai, semiconductor-related companies already located there are well positioned to exploit new business opportunities — opportunities that depend on proximity to their end-user customers.

To fully capitalize on the regional opportunities, major players in the semiconductor industry are evaluating and, in some cases, implementing plans for expansion and greater presence in China. For example, AE is expanding with a significant manufacturing facility in the Guangdong province. Top companies are finding that increasing manufacturing commitments in China increases product quality because of the proximity to world-class, tier-one suppliers; decreases delivery time, enhances response time, and provides better supply-chain management because of the proximity to customers; and decreases production and operational costs because manufacturing costs are lower.

Visionary companies are expanding and strengthening their presence in China. Close proximity to both suppliers and customers enables these companies to exploit emerging opportunities — to the benefit of their customers.

This year's SEMICON West should prove interesting on many fronts as the equipment industry is slowly coming out of its longest downturn ever. Great disparity often fosters great innovation. This year will mark the turning point in test, as we move toward implementing the concept of a cooperative, open architecture.

No longer is it a question of whether or not to adopt an open architecture for testing complex, advanced ICs. Now the issue is: How do we best implement this open architecture? This concept — launched last year at SEMICON West with the establishment of the Semiconductor Test Consortium (STC) — will provide end users with a universal framework into which virtually any ATE supplier can integrate its compatible modules to create a highly customized test system.

This new approach offers a projected life of more than 10 years — compared with today's test systems that become obsolete in just four to six years. I expect that this open-architecture test solution will help temper future swings in the industry's cyclicality and provide end users with a highly simplified, sophisticated test solution that will reduce the cost of testing complex logic, mixed-signal and most types of system-on-a-chip devices.

Equipment companies will continue to experience direct and indirect effects from the technology growth in China. Western IC foundries are seeing a drop in demand for non-niche technologies because of price and capacity competition from Chinese fabs. As a result, demand for equipment from Western manufacturers will continue to slow. Though the Chinese fabs take up much of this demand, equipment prices for sales to China are falling. These prices will continue to erode, perhaps to a point lower than the industry can bear.

We'll see increased consolidation and closures of equipment companies in the near future as they struggle to maintain profitability in this new pricing environment. Equipment companies supporting or manufacturing niche and leading-edge technologies may be best suited to survive this shift in demand, as Western foundries will continue to receive those types of IC orders.

The transition of CMOS semiconductors to low-k dielectric materials at the 130 nm node is not only a device design and wafer fabrication issue, but has significant implications for IC packaging technology as well. Packaging processes and materials that have been used successfully in the past can put unacceptable levels of stress on fragile new dielectrics, which could lead to delamination between device metal layers.

Optimized wafer dicing, wire bonding, and encapsulation processes, together with generally lower-stress packaging materials, are part of the solution. However, one must also consider other factors such as the interaction of the package with die passivation, pad structure and corner seal ring design. Different package structures impart different levels of stress to the device. At the same time, different device structures exhibit varying levels of fracture strength.

With reduced internal stress design margins associated with low-k dielectric materials, significantly increased levels of cooperation between wafer and packaging engineers are required in order to bring advanced products to market quickly. Challenges associated with packaging these next-generation devices will continue to increase as metallization becomes even finer and capacitance is managed with even lower-k dielectric materials.

With every major equipment company cutting back to cope with the continued downturn, I would expect SEMICON West to be even leaner this year. There will be fewer companies exhibiting, fewer people in the booths, fewer tools, and likely fewer customers in attendance.

When we look at where to allocate resources, we are always focused first on providing the continued support and product innovation that our customers require. At the same time, we must continue to stimulate marketplace interest in our products and capabilities, because it is only through growth and profitability that we continue to fulfill the customer mission. For us, SEMICON West is an important opportunity to showcase our latest technologies. We are simply finding new ways to accomplish the same goal more efficiently.

Despite continued economic uncertainty in the market, we believe SEMICON West 2003 will bring some positive news — specifically in the area of low-k dielectrics integration for dual-damascene designs. The semiconductor industry has been grappling with the adoption of low-k dielectrics for the better part of the last decade, with some of the most challenging aspects involving the integration of these new materials with existing fabrication processes. Low-k dielectrics can only improve device performance if chipmakers have tools and processes that work with these sensitive materials. This is especially true when it comes to conventional back-end-of-line cleaning processes, which can cause latent damage to low-k films, leading to changes in the material's k_eff value and structural integrity.

The good news is that equipment and materials suppliers are succeeding. For example, by working closely with low-k suppliers and our customers, Axcelis has developed a dry strip system that won't damage dense or porous low-k films. The real significance of these developments is they allow chipmakers to focus less on process compatibility issues and more on improving overall productivity.

As new 300 mm fabs come up to speed, both the fabs and equipment manufacturers are facing the problems and effectiveness of the 300 mm automation interfaces, which are more often than not a result of the implementation challenges associated with the standards. Cimetrix has focused its effort on creating robust software to help equipment suppliers meet the new 300 mm standards and direction from SEMI, ITRI and the Global Joint Guidelines.

Over the last year, by working directly with the fabs, we have learned that new equipment compliance to the 300 mm standards is not meeting the expectations of the fabs. As a result, we will see new products aimed at removing the complexity of this task and providing reusable software components for the equipment supplier. However, as an industry, we must also put more importance on good software development methodologies, as semiconductor equipment becomes more software-intensive.

Our discussions with the fabs have also created a clearer picture for equipment data acquisition (EDA), and how e-diagnostics, using EDA, is progressing from an overused buzzword to actual pilot projects that make sense. Having equipment suppliers create their own e-diagnostics solutions doesn't make sense from a fab standpoint. Data security cannot be achieved with a hundred different approaches. This must be driven by further evolution of the standards and by the fab's infrastructure.

As we progress toward the 90 and 65 nm technology nodes, the emerging material issues are high-k gate dielectric, metal gates, and SOI. Of course, low-k dielectrics are ready to go. Investments in low-k dielectrics have delivered spin-on and CVD solutions in the k=2.7 range. Beyond that range, porosity remains a key issue to solve.

Memory devices have a long history of using spin-on dielectrics with constants around 3.0. Currently, devices with low-k and SOI are in limited production. There will be a growing trend toward a hybrid of dielectric solutions, combining low-k with standard dielectrics, which will lead to full stacks of low-k devices. These hybrids will enable an entire new generation of microprocessors with processing power beyond 3 GHz and well into the 5-10 GHz range.

Whether handling known-good-die on a film frame or packaged devices assembled on strip, the ability to handle and test large arrays of packaged devices in parallel for final test can deliver tremendous improvements in overall throughput by bringing the efficiencies of the front end and wafer test to the assembly and final test area. This method of test handling will enable the trend toward continually reduced package dimensions, which are critical for both smaller end product packaging, as well as high-speed devices, and will help with 3-D packages that feature multiple die stacked on top of one another. More importantly, matrix handling for final test applications will help chipmakers reverse the trend in which assembly and test has been increasing in relative cost compared with overall fab costs.

Yield and reliability at 130 and 90 nm nodes are serious concerns of fab managers today, and an emphasis that we expect to see this year at SEMICON West. FEI addresses these issues by providing fabs with the 3-D structural process control solutions needed to enhance yield and reliability as feature sizes decrease from 130 to 90 nm nodes and beyond.

The imminent "end of conventional VLSI scaling" (Moore's Law scaling) marks the inflexion point where traditional silicon scaling becomes limited and a need to integrate new and novel materials into VLSI processes becomes the norm. This phenomenon, coupled with reduced process window margins, pushes the need for real time 3-D metrology and monitoring. As VLSI process features become smaller, the device performance becomes significantly more dependent on the total shape (3-D) of patterned structures, and traditional top-down measurements do not adequately correlate to electrical performance.

In today's market, IC manufacturers must drive down cycle times to remain competitive. Coupling this requirement with the emergence of new materials and smaller geometries creates an interesting challenge. For example, in the cleaning arena, we are challenged to create solutions that include damage-free cleaning of gates, cleaning low-k dielectrics without altering the k value, and high-k dielectric processing, while simultaneously addressing productivity issues such as short cycle time and cost of ownership. How to approach these challenges is fueling industry debate in the batch vs. single-wafer cleaning arena.

FSI's 30-year history of providing surface conditioning products makes us acutely aware of the need for different wafer cleaning approaches and the consequent drive for different technology solutions. We take the stance that both batch and single-wafer techniques are here to stay, complementing each other to serve the complete range of wafer cleaning requirements.

Copper barriers for 130 nm devices are primarily composed of a single, relatively thick layer of tantalum or TaN. Monitoring is done in one of two ways: sheet resistance metrology, a method that requires physical contact with the wafer; and/or photoacoustic metrology, which sends a pulse through the film and measures the transit time of the signal. These techniques will be unable to reliably measure the much thinner (10 nm) bilayer barriers — composed of tantalum and TaN — needed at the 90 nm node.

With acoustic metrology, measurements become unreliable with thinner films as the transit time becomes too short and the copper seed layer washes out the signal from the underlying barrier layers. Off-line metrology methods such as Auger, SIMS, RBS or EPMA are well utilized today for 90 nm process development of copper barrier films. Once barrier processes are moved into production, however, chipmakers are literally flying blind — with no cost-effective or production-worthy method of monitoring copper barrier composition and across-wafer uniformity.

A clear and present danger stalks the semiconductor industry on the eve of SEMICON West 2003. The mask cost burden for advanced low-volume applications, typically running 100 wafers and yielding 100 good die per wafer, can be $2600/wafer or $26/die at the 180 nm node, and $10,000/wafer or $100/die at the 90 nm node. Advanced chips are more likely to need multiple iterations. This cost burden is stifling the industry's productivity and reducing the number of new designs being introduced.

The industry will begin to turn to maskless optical scanning to optimize chip yield and speed. A single optical maskless scanner can save as much as $50M in mask cost annually at the 130 nm node and more than $100M for the 90 nm node. And the technology is available today to develop such a system. Reducing mask costs and manufacturing time will lead to more new design starts, resulting in new innovations.

The photomask remains the most effective method for high-volume applications. But if we do not reduce the cost for new designs and low-volume applications, the industry will compromise device performance for cost. The semiconductor will move from a technology enabler to a mere supportive role in technology.

As we approach SEMICON West 2003 it is startling to consider that our industry has been talking about implementing e-diagnostics and advanced process control (APC) of process tools for almost 20 years. This is the long-discussed next step up the value chain. Unfortunately, it has remained more talk than action. That is set to change. At this year's show, you'll see that e-diagnostics requires more than "genius software." It requires high-quality data supplied to that software and to users on the factory network. We will see that critical enabling technology for e-diagnostics — smart sensors surrounding the process chamber — is finally in place.

Information is the key to e-diagnostics, and today's smart sensors, integrated into OEM subsystems, will help transition e-diagnostics from inefficient data mining to a far more time- and cost-efficient extraction of "actionable" data.

MKS is at the forefront of enabling e-diagnostics that will have a powerful impact on semiconductor manufacturing efficiency. The move to provide digital information in real time for manufacturing networks will also impact manufacturers' yield and profitability. In addition to providing high-quality sensor data, we are correlating it with wafer identity using our BlueBox connectivity product.

As manufacturers move to sub-100 nm feature sizes, we believe that optical critical dimension (OCD) measurement systems will emerge as the key solution for CD measurement. Scanning electron microscopy (SEM) systems are now reaching their sensitivity limit for these smaller circuit dimensions, and OCD is strategically poised to dominate this market segment.

OCD technology is accurate, precise and non-destructive, and can provide measurements of linewidth, pitch, step height and line profile in real time. Conventional CD-SEMs cannot measure line profiles, and their accuracy depends on image processing settings. In addition, the electron beam may damage the test area, and the measurement is time-consuming, labor-intensive and made in a vacuum, which makes it nearly impossible to integrate into a process tool.

The need for very tight process tolerances and productivity improvements in fabs is driving the demand for APC, and integrated OCD solutions are an enabling technology for APC. The compact size and speed of this new OCD technology enables the measurement system to be fully integrated into the process tool, thus providing a complete, high-throughput, feedforward and feedback APC solution for wafer-to-wafer closed loop control.

With most of the industry now settled on fluorinated silicon glass (FSG) films for 130 nm production, semiconductor device manufacturers are considering their options for low-k dielectrics at 90 nm and below.

While the semiconductor industry trade press continues to focus on bulk intermetal dielectric (IMD) films with k values of <3.0, these offerings failed to gain commercial acceptance at 130 nm because lowering the k value was chosen over maximizing the hardness of the film. The end result is soft materials that led to packaging failures. Because of this experience at 130 nm, the industry focus has now shifted to 3.0 films with a hardness of >2.0 GPa for 90 nm production.

Looking ahead to 65 nm, the challenge will be to lower the k value without creating a porous material, while maintaining a hardness of ~2.0 GPa. Porous materials are unlikely to gain wide acceptance for 65 nm production. This is largely because of the very low hardness and the complexity of dealing with the porosity — issues that can easily lead to integration schemes that increase the overall k value of the dielectric stack (k_eff). Choosing the right option is likely to become one of the more interesting debates in interconnect technology over the next year.

With continued uncertainty in the marketplace, the upsurge in end demand remains elusive. Absent the demand pull, chipmakers and suppliers alike are seeking ways to improve financial health. As suppliers, we can support our customers in this effort in three ways: improvements in productivity, reduced cost of ownership and solutions to technical problems.

Success in any of these endeavors requires partnering with our customers. Our experience in copper and low-k dielectrics has shown that each fab has different integration schemes, process budgets and material choices. Collaboration between the supplier and the fab process engineers is mandatory to develop and deliver the materials and processes that can address the cost, productivity and technical challenges within that fab. Cross-collaboration with other suppliers will also improve the odds of a successful implementation and reduce the risk of adoption of new technologies.

Relentless attention to quality and supply chain excellence can also help drive system costs down. The discipline and improvements made today for cost reasons can help the near-term financial situation. Equally important, however, is that when the demand finally does resume, both the fabs and the supply base will be better positioned to meet it.

SEMICON West 2003 will showcase advanced metrology technology for the 90, 65 and even 45 nm nodes, although capacity tool buying for the next production peak will be at 130 nm. Successful metrology vendors must concentrate their R&D resources on both existing challenges and those two or more generations ahead. If vendors select the right technologies, metrology tools will be available to enable manufacturers to qualify their next-generation processes. When production ramps, metrology suppliers will be rewarded with purchases of their production-worthy yield-enhancing tools.

Current metrology challenges include enabling successful integration of copper metallization in low-k dielectrics; smaller, faster advanced gates — nitrided and high-k gates; strained silicon for speed and SiGe for wireless; automating macro defect inspection for lithography; and integrating metrology modules into critical process steps

Despite the current economy, there are some favorable dynamics for metrology vendors. Newer materials and design shrinks are causing device makers to spend more money per fab for metrology to keep advanced processes under control. The higher cost of process excursions is also driving metrology growth. The industry is increasingly convinced that metrology is a value-added process. Investment in metrology saves chipmakers money and leads to higher yield and profits.

As the semiconductor industry transitions to 300 mm manufacturing, increasingly smaller geometries and new materials, manufacturers are reevaluating their wafer cleaning methods. The wet clean market, traditionally dominated by wet-bench or batch processing, is undergoing a significant shift in technology focus. Larger wafer sizes and shrinking design geometries are driving semiconductor manufacturers to select single-wafer wet clean processing to minimize cross-contamination during critical cleans. As a result, we expect the market segment for single-wafer wet-clean systems to grow from 20% to 32% of the entire wet-clean market by 2006.

Although batch processing still dominates front-end-of-line (FEOL) cleans, especially for nitride and oxide removal, resist strip and high-/low-k material removal, backside applications are predominantly single-wafer, as are 40% of all back-end-of-line (BEOL) cleans. As the industry transitions to 65 nm manufacturing, logic makers are expected to lead a shift to FEOL single-wafer cleans, with memory providers following suit as single-wafer tool cost of ownership improves. As a result, we anticipate an imminent dramatic upswing in evaluation of single-wafer cleaning solutions for use throughout the entire semiconductor manufacturing process.

Although we might not occupy as much floor space at SEMICON West 2003 as our confreres in equipment, purveyors of materials are now at the center of innovation. SOI, sSOI, low-k, high-k — all put materials in the spotlight.

This shift ushers in the new era of the three-party relationship: The chip manufacturers and the equipment vendors are now joining forces with the materials suppliers. Both at the conferences and on the show floor, the talk will center on the integration of new materials, and the announcements of partnerships to support these moves.

We are clearly among the beneficiaries of this new paradigm. With the 65 nm node now in sight and decreased power consumption a top priority, leading chip manufacturers recognize the value of giving us insight into their processes and needs, current and future. This enables us to engineer advanced substrate and heterosubstrate solutions tailored to specific applications — be they low-power, high-power, high-speed or convergent. Likewise, the equipment vendors are working closely with us to optimize the requisite process technology. Integration of new materials is always a challenge, and the current stretch in the drive to smaller geometries involves new materials at every turn. But, unlike the moves to copper and 300 mm, the new material challenges are being met by partnerships of all concerned parties.

While in parallel the industry will continue to search out new venues for economic innovation (such as the foundry model and the rise of manufacturing in Asia-Pacific), there is still plenty of room for differentiation through technology. In the quest for high volumes and lower costs, innovation is still the most powerful tool we have. At this year's SEMICON West — and for years to come — materials will represent the core of innovation that drives us forward.

The maturation of MEMS-based technologies continues to transition from an "emerging market" to one increasingly requiring volume production. Increased focus by equipment suppliers on this market segment is anticipated at SEMICON West as companies recognize this transition and look for revenue streams to help offset the extended mainstream market down-cycle.

MEMS devices are maturing in terms of the methodology used for manufacture — transitioning from R&D and pilot-based production environments to real production volume-oriented facilities.

This transition represents a significant milestone in the development of the MEMS market segment on the overall path technology-based products typically follow — the transition from a "technology push" environment to one of "market pull." This means that the challenge posed to both the MEMS device manufacturers and their suppliers will become the cost of manufacture as opposed to the solution of technical problems. "Fulfilling the technology node at the lowest cost per die" will progressively displace "technology improvement at any price."

This was a maturing process historically observed in the mainstream IC business and it is now the case for MEMS technologies. The time taken for this transition will somewhat depend on companies' current understanding of this historical perspective and the extent to which the transition itself has been anticipated. Market forces will start requiring significant attention to throughput, cost and reliability, while maintaining technical capability.

An important trend we see leading into SEMICON West 2003 is growth in new process technology investments, especially for advanced power device fabrication — driven by the growing wireless communications industry. Of particular interest is the increasing need to process these devices on thinner and thinner silicon substrates. Ultrathin substrates in power device fabrication enable transistor operation at lower junction temperatures, creating significant improvements in device efficiency and reliability.

Since power transistors represent some of the most expensive IC components for cellular power amplification, keys for success in this market are controllably depositing low-stress metallization films while maintaining reliable wafer handling, high throughput, and low cost of ownership for substrate thicknesses down to 85 µm and thinner.

Through our PVD equipment arm, Sputtered Films Inc., we are experiencing a marked increase in demand and process expertise for metal film deposition on ultrathin substrates. Similar to new approaches for memory devices, such as MRAMs and FeRAMs, we are seeing a stronger push for faster advances in processing technologies.

In the consumer electronics space, we expect the trend toward multi-component packaging (MCP) to continue to gain momentum, with cellular handset makers leading the industry as early adopters. Market research firm In-Stat/MDR predicts that Internet-enabled device shipments, including mobile handsets and PDAs, will increase from 430 million in 2002 to ~760 million in 2006.

To protect and expand market share, OEMs are calling for technologies that enable increased system integration, enhanced functionality and reduced product size. While two-die stacks continue to play an important role in achieving higher levels of integration, MCPs that can accommodate up to five die, and allow for the combination of memory, logic and other functions, represent an exciting new development area with significant market potential. However, there are business and logistics issues that are impeding the broader adoption of these more highly integrated packages today. Solutions that help to overcome these issues will be well positioned to achieve long-term market success.

A developing trend in the wireless space involves the use of advanced packaging technology in the rf domain, where integration has been more difficult to achieve because of the large numbers of discrete components and the unpredictable nature of rf.

We expect MCPs of a number of varieties to continue to gain market acceptance and momentum. Ultimately, we expect the industry to converge on a select few that best meet the integration challenge at the lowest possible cost.

Throughout this extended industry downturn, leading-edge companies have searched for ways to maintain their technology leadership positions. This SEMICON West will bring to light new, innovative technologies that will be rapidly adopted by the top technology performers.

One such example that will be discussed at the show is the replacement of rapid thermal processing (RTP) with a revolutionary technology known as laser thermal processing (LTP). Conventional rapid thermal annealing has evolved to shorter times and higher temperatures to limit transient-enhanced diffusion and improve dopant activation. Current spike annealing technologies achieve sub-100 msec exposures near peak temperatures of 1100ºC. However, further scaling of this lamp-based technology appears to be difficult.

Laser-based technology has created an entirely new category of semiconductor processing by combining projection optics and lasers for the purpose of thermal annealing.

Laser thermal processing is designed to break through process barriers associated with advanced junction and contact formation at 90 nm and below. LTP is capable of achieving activation in the nanosecond through millisecond timescales and is ideally suited to replace RTP for leading-edge annealing applications.

The continued emergence of China as a global semiconductor industry player is a trend that will affect SEMICON West 2003 and be an industry driver for several years to come. The energy and excitement in the Chinese semiconductor community is reminiscent of other nascent semiconductor industries in the Asia-Pacific region in decades past (Korea, Taiwan, Singapore). The evolution is likely to follow a predictable pattern: starting as low-cost suppliers and developing into cutting-edge technology leaders.

The good news for our industry is that each time a new country has launched a major drive into the semiconductor industry, the industry has grown along with the new entrant. It is critical that the industry be mindful of the lessons learned during the rise of other Asian industry players and take advantage of the opportunities offered by China's rise as both a manufacturer and consumer of semiconductors.