New Method Reduces CMP Data
Peter Singer, Editor-in-Chief -- Semiconductor International, 6/1/2003
A new method has been developed by researchers at
SpeedFam-IPEC (a Chandler, Ariz.-based company that was recently acquired by Novellus) that simplifies the process of relating feature-scale performance metrics such as dishing and erosion to wafer-scale non-uniformity during chemical mechanical polishing (CMP). The new method was presented in the April issue of The Journal of the Electrochemical Society.
"Process development is a costly and time-consuming engineering effort for CMP consumables and equipment manufacturers," said Thomas Laursen, one of the authors. "CMP process development involves optimizing different aspects of the polish such as polish rate and non-uniformity, planarization and defectivity. Improved process characterization — which results in increased accuracy and reduced cost — will contribute to a more efficient process development. Our paper describes an improved method for organizing and collecting feature-scale planarization (FSP) data for CMP processes."
Traditionally, the FSP of a CMP process has been obtained by collecting total indicated range (TIR) data as a function of polish time for representative die. However, the Novellus paper shows that fundamental planarization behavior is best described by an FSP plot displaying TIR vs. copper thickness data. "The most important aspect of this data organization is that it provides a simple method to separate the FSP from the polish uniformity," Laursen said. "This can improve the accuracy of the measured planarization behavior, particularly in cases where the data can be based on direct measurements of the copper thickness on the die locations being characterized."
Using FSP plots based on copper-thickness data, accurate planarization can be measured for CMP processes that are not fully optimized. This reduces the process development time required for process screenings and, in addition, it minimizes resources by providing a comprehensive FSP characterization curve from incremental polish of a single pattern wafer. Separating the planarization from the polish uniformity has the added advantage of relating the polish uniformity and dishing and erosion requirement in a simple way, e.g. by a graphical method using the FSP curve.
The Figure is an FSP plot of a local trench feature, where TIR is shown as a function of field copper thickness (note that the copper thickness abscissa is reversed so that the polish removal proceeds from left to right). The two triangular points represent measurements that are taken before and after the polish. These two points establish the locations of two "reference lines" that represent idealized polish performance. The left reference line corresponds to the idealized performance where only the up features are polished. Therefore, it has a +1 slope. The right line corresponds to the idealized performance during and after clearing where only the copper in the trenches is polished with the same removal rate as before clearing. Therefore, it has a -1 slope. The leftmost data point represents the initial copper thickness and trench depth. In an idealized polish that follows the reference line, only the top part of the up features is reduced. They become planarized at what is labeled the planarization-onset point. The right data point represents complete removal or "clearing" of the copper in the field areas. As the copper clears in the field region and can no longer be measured at all places on the wafer, the abscissa is determined by extrapolating the copper thickness values determined from local copper thickness vs. time plots. When the field copper clears locally, the field-copper thickness is zero; when the field copper is being overpolished, extrapolated copper thickness becomes negative, indicating how much copper would have polished had it not already been cleared.
Laursen said a second aspect of the FSP plot using copper-thickness measurements on selected die is that the curves obtained ideally coincide. To the extent they do deviate, this quantifies the die-to-die variation of the planarization.
A third aspect of the FSP plots — being based on length parameters — is that they can be directly related to the copper deposition and its parameters such as copper thickness, trench depth and super-fill thickness. "Having removed the time dependence of polish rate and clearing non-uniformity, the FSP curves display effects of pad bending, overpolish sensitivity and clearing offsets by referencing the data to idealized polish behavior. The graphical visualization of these effects facilitates the understanding of the planarization behavior and can related to models such as MESA."
For additional information on wafer processing, go to www.semiconductor.net/wafer.
