Foundry Addresses Broad Range of Reliability Requirements

Appearing as a keynote speaker at the 2003 International Reliability Physics Symposium, Shang-yi Chiang of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) emphasized the myriad reliability requirements of its many customers, with particular emphasis on low-k dielectric breakdown, advanced process control (APC) and in-line measurements as well as design-for-reliability. Chiang is senior vice president of R&D at TSMC, and was recently cited as a Star of Asia in Business Week magazine.

Of course, foundries face the same reliability and yield challenges as integrated device manufacturers (IDMs). Chiang particularly addressed the challenges the industry's leading foundry faced in going from the 0.18 to 0.13 µm generations. He admitted that, during the early stages of low-k dielectric implementation, dielectric reliability testing (time-dependent dielectric breakdown) did not meet specification. In addition, the conductivity of low-k dielectrics is a factor of three times poorer than that of oxide and fluorinated silicate glass (FSG), which can lead to electromigration problems.

However, stress migration proved to be the greatest interconnect challenge. "One of the most painful experiences we had was stress migration as we went to 0.13 µm," Chiang commented. One specific problem was the formation of copper voids under vias, especially those connected to wide metal lines. "One solution is to make multiple vias when you have a wide metal," he said.

He added that the temperature of stress testing must be carefully optimized because of copper's sensitivity to temperature change. "There's a balance between stress and diffusivity. At room temperature, copper is under high stress, but the atoms are not very mobile so they stay in place. As the interconnect heats up, stress is relieved but copper becomes a faster diffuser. So there is an optimal temperature at which to do stress testing, which also depends on interconnect dimensions."

To control reliability in general, Chiang explained that APC is becoming more important, using statistical process control (SPC) with feedforward and feedback control for critical processes. Feedforward/back control is crucial to improving Cpk and yield. He commented that, usually, when Cpk is improved, reliability improves as well.

Chiang estimates that, when all is said and done, TSMC will offer roughly 100 processes in the 0.13 µm generation alone. "For 0.13 µm logic devices, we offer eight transistors with others available through special request of our customers," Chiang said. Part of the challenge for foundries is meeting the requirements of as many device types as possible. Chiang believes that the experience his company has with a variety of device types gives it an advantage in the burgeoning system-on-a-chip (SoC) market. TSMC offers the ability to integrate logic, mixed signal/rf, embedded memory and more. Foundries first perform process qualification, then aid customers in the product qualification stage to ensure quality and reliability upon application of the foundry's process.

Design-for-reliability is becoming increasingly critical to a company's bottom line. It refers to the consideration of reliability as early in the process as possible because the later that reliability problems are addressed, the greater losses companies have in lost time-to-market due to delayed ramp to production. "We try to provide designers with a list of guidelines for better yield and reliability, and for each process module we try to understand reliability issues," Chiang said.

TSMC is on track to deliver its first 90 nm generation devices later this year.

For additional information on yield management, go to www.semiconductor.net/yield.