Low-k Integration Advances With Hesitation

The industry has exhibited a love/hate relationship with low-k implementation. Reticent to change processes and devastated by the downturn, it has attempted to work around low-k dielectrics, knowing that eventually it will have to embrace them.
 
Brian Daniels, director of thin-films technology development at Honeywell Electronic Materials (Sunnyvale, Calif.), believes that low-k developments echo those of previous years. "The industry pushed out low- and ultralow-k. Competition between spin-on dielectrics and CVD in some 130 and 90 nm technologies gives CVD preeminence. As we advance to other nodes, the question of CVD vs. spin-on will still be in evaluation. At 2.2 and below, we face problems common to both platforms."

"The industry isn't gated by how low low-k can go, but by what a low-k film's practical limit is, which I estimate at 2.2 or slightly below," said Farhad Moghadam, vice president and general manager of the dielectric systems and modules group at Applied Materials (Santa Clara, Calif.).

Mike Gallagher, ILD program manager at Shipley Microelectronics (Marlborough, Mass.), sees issues with various CVD and spin-on products integrated at 90 nm. "Users look to material suppliers for integration solutions. As k values decrease, material density follows, whether the material is deposited by CVD or spin-on. Reduced density presents challenges during the integration of ultralow-k materials, including photoresist poisoning, plasma and wet chemical damage, barrier sealing and mechanical integrity. The latter has caused issues with CMP and device packaging."

According to Moghadam, interest previously centered on implementing low-k at 130 nm — now it is on FSG. "FSG will be used at that node. Low-k will go into production this year, although the market downturn and some integration issues have delayed implementation."

Integration issues seem more user- than process-flow-specific. "Do I use low-k on all layers or in four or five, and FSG for the top two layers?" Moghadam asked. "With any low-k, you may run into reliability and C4 packaging problems." Users must also change toolsets or processes. "One just doesn't drop low-k with FSG and expect it to survive — the film isn't as chemically or mechanically strong as FSG or undoped oxide," he added.

Mechanical properties are low-k's chief modulator — strength, hardness modulus, cohesive strength and fracture toughness. "If you plot k values vs. hardness, there's a trade-off between how low a low-k you can attain and the mechanical properties you relinquish, leading to CMP problems, film cracking, etc.," Moghadam explained. Integrating k<2.0 porous material is difficult — vias must be etched and sidewalls covered with thin barrier/seed layers. There is interaction between low-k porosity and the barrier's coverage, especially on via sidewalls. "You can design a couple of layers without low-k, but ultimately you must integrate it," Moghadam said. "Sometimes, in ILD 1, people use regular SiO₂, not even fluorine-doped materials. They design short metal lines, upping performance through resistance reduction, and don't depend on capacitance reduction, eliminating the need for low-k."

ASM Japan (Tama, Japan) developed its low-k CVD film specifically for 90 nm technology. "It borders 2.9, 2.8 k, with pores 6-7 Å in radius, minimizing water absorption and yield degradation after integration," said Tominori Yoshida, PECVD business unit manager. "We've demonstrated a k value of ~2.5 for the 65 nm node, but the number of pores/cm² for the 65 nm film is 50% higher than for the 90 nm film." Although water absorption is stable due to small pores, the material is softer, and some integration issues remain.

"Promising results have been obtained with 2.3 k-value films for the 45 nm technology node," Yoshida said. "Higher porosity — same pore size; however, they're softer and mechanical properties must be improved. We're initiating different chemical structures in the film and testing precursors to optimize mechanical properties. Another approach is a post-deposition treatment such as UV or electron-beam annealing, which almost doubles mechanical hardness. For 65 nm we expect a 2.5 low-k film with 1 kPa hardness, and a >10 kPa modulus. However, the technique may cause shrinkage, reduce cohesiveness and damage transistors."

Chris Werkhoven, vice president of strategic marketing at ASM (Phoenix), views the 90 nm node as the first entrance point for CVD films. "At 130 nm, there wasn't enough experience to replace FSG. SOD had a much earlier exposure in the industry, but usage is limited to a few companies. Now, CVD films dominate because of better mechanical properties that enable integration — including encapsulation — with high yield and at acceptable costs."

FSG has nine lives, said Ravi Laxman, global product manager for low-k products at ATMI (San Jose). At 130 and 90 nm, there's an evolution toward k=2.8 carbon-doped SiO₂, using primarily 3MS or DMDMOS precursors. "Carbon-doped SiO₂ use will probably continue to at least 65 nm. The issue isn't k value — people deposit low-k films with varied precursors — it's integration."

Neil Hendricks, ATMI's chief technologist, said that his company is prepared to support CVD low-k, because it appears that spin-on may not take off. "We must recognize that the JSR ultralow-k and its competitors in the 2.2 k realm are still futuristic materials. We put a graph together to see what low-k would be, vis-à-vis the precursor. From a PECVD perspective, it shows the k value has a 2.8, 2.7 limitation, regardless of precursor. We may hit a wall after 2.5. We'll probably remain in this evolutionary phase between 2.8 to 2.5 well into 65 nm."

"Roadmaps are delayed, FSG's life span has been extended, and it's unlikely anything else will be used in widespread production at the 130 nm node," said Keith Buchanan, process integration manager at Trikon Technologies (Newport, UK). "The general trend at 90 nm is to use CVD materials with ~2.8 k values. Despite integration issue delays, the adoption of low-k materials with <2.5 k values could be realized at the 65 nm node. We've been successfully working with a number of leading manufacturers on integrating our 2.5 and 2.2 films into 65 nm device schemes."

Trikon believes that, irrespective of which low-k material is used, a considerable part of the problem is mechanical. This is causing difficulties in integrating co-processes such as CMP, and possibly more serious issues like stress migration. Short-loop testing, an expensive process that imposes empirical work, cannot be done in these situations (nine and 10 levels of metal must be built to discover them).

Since the 1990s, SEMATECH has identified more than 100 low-k candidate materials. "Issues arise when you must solve how to pattern and etch it, then how to clean, metalize and polish it for 10 levels of interconnect," said Mark McClear, global business director, semiconductor fab materials at Dow Chemical (Midland, Mich.). "Afterwards, there's packaging and testing. Thus, proposed materials fall by the wayside." He sees two left: SiLK and CVD.

1. Barriers on porous SiLK have been proven. Seen here is the compatibility of PVD barriers with porous SiLK films: complete sidewall coverage over a closed-pore system, using low-resistivity alpha-phase tantalum. (Source: IMEC)

At Dow Corning (Midland, Mich.), the main effort is focused on CVD — the strategy being to design molecules that the industry believes meet the process needs, said Mark Loboda, associate research scientist. "As far as spin-on technology goes, we can meet the long-term nodes that require k under 2.2, but the equipment infrastructure isn't there. Because of this we've reduced effort in that area compared to our CVD effort."

Though Dow Corning develops processes that fit porous and non-porous strategies, Loboda is not a fan of the infatuation with porous testing. "When talking about low-density materials, there's not much to learn discussing pores. If I take a thick cloth and stretch it out, density is reduced without pores. It's the same with low-k materials — we stretch out Si-O-Si bonds compared to SiO₂."

According to Daniels, Honeywell is developing low-k materials and considering enabling technologies to make low-k work. "Whether a CVD or spin-on deposited film, it must be porous to get a k of 2.4 and below. We're investigating how to deal with a porous film and put a barrier on it. But porous film encompasses many things: barrier adhesion to that interface, if you move to an ALD- or CVD-deposited copper diffusion barrier encompassed in there, as well as carbon depletion issues. There are challenges to CVD and spin-on that we're working on to enable either one."

Low-k implementation is a perennially "imminent" process, according to Eric Johnson, COO at JSR Micro (Sunnyvale, Calif.). "The roadmap has slipped for seven years. Integration points of low-k in general and spin-on in particular have been pushed out. Our material was evaluated and accepted as the baseline material for SEMATECH's program. However, now the problem is getting momentum for integration. It isn't CVD vs. spin-on; it's how to move from what you're doing to something new. There are many low-k implementation options. There are design changes that'll postpone it. There's viable low-k implementation to at least 45 nm. With 90 nm there isn't much opportunity for spin-on materials. We see 65 nm as a battleground and 45 nm as volume opportunities — a ramp for spin-on low-k material."

Wilbert van den Hoek, CTO and executive vice president of integration and advanced development at Novellus (San Jose), sees a move to 90 nm volume production. "After failing to go to volume production using low-k materials with a k<3.0 at the 130 nm node, at 90 nm over half the industry will implement a ~3.0 k material in their copper low-k interconnect."

The implemented film is different from the one considered for 130 nm, when the intent was to reach 2.7, disregarding hardness. "Typically, hardnesses were on the order of 1.0 GPa," van den Hoek said. "Those films didn't survive packaging, causing everyone to back off on k values. What you're seeing implemented in 90 nm is typically k=3.0-3.1 films, with >2.0 GPa hardnesses."

At the 65 nm node, porous ultralow-k adoption has been delayed. "Based on lessons learned at 130 and 90, we won't go to porous low-k because the mechanical properties wouldn't allow successful integration," van den Hoek explained. "At 65 we'll return to 2.6, 2.7 low-k material, leverage the learning that drove up k=3.0 film hardness, and attempt a hardness of ~1.5 GPa and a 2.6 k."

At the 45 nm technology node, 70 nm line/space, a dense dielectric (kbulk~2.6) offers higher performance (equal C and lower R) than porous dielectric (kbulk~2.2). Assumptions: 40-nm-thick SiC dielectric barrier with k~3.5, effective resistivity is a function of linewidth. (Source: Novellus)

To retain the ultralow-k nature, a sealing process that avoids putting 3-5 nm of "high-k" material of metal barrier over the pores — without it penetrating the porous low-k film — is needed. In future nodes, capacitance may have to be lowered through design rather than material — diagonal interconnect is an example.

Shipley's Gallagher believes that barrier deposition will be important at the 65 nm node and beyond. "Laying a thin uniform barrier is key. Uniformity is critical; otherwise, you have defects or stress points, and non-uniformities will result in loss of barrier integrity due to copper electromigration and loss of low conductor resistivity."

For uniform barrier layer deposition, pore sealing or other methods may be necessary for a smooth interface on the dielectric material's surface. Engineering this interface is critical because all materials — CVD and spin-on — have intrinsic free volume or microporosity (even the k=2.7 dense films). "As k value and density decrease, surface roughness increases, contributing to barrier non-uniformity," Gallagher said. "There have been improvements in device design and in low-k film processing, where the material's overall k is reduced by eliminating cap layers and changing the integration process. However, the trade-off is increased process complexity. There'll be a need, probably at 65 nm, for materials with lower effective k values, which implies porous materials."

Shipley sees a need to further develop materials with enhanced capabilities, along with necessary process modifications. "We've developed dielectric material based on a polymeric porogen with thermal stability that allows integration through the fabrication steps for an entire metal level, including CMP, and then removal through special spin-on hard masks," Gallagher said. "Instead of working with a material with the porosity required to achieve 2.2 or 2.0, we're integrating a solid dielectric material."

The porogen-containing dielectric has been processed through several integration steps: etching, plasma, wet chemical treatments, barrier deposition and CMP. "If we deposit an ultrathin TaN layer, we're able to seal the film," Gallagher explained. "Standard etch processes work; porous zircon etch, and plasma and wet chemical treatments don't change the structure; and films survive CMP without delamination, scratching or peeling." The porogens decompose at 300-400°C. By processing the material below that temperature, they remain intact in the film until they are ready to be removed, and can proceed to the next layer. "We use a spin-on hard mask layer with enough microporosity to allow polymer decomposition gases to pass through, leaving a protected porous material," he added.

Mark O'Neill, thin-films technology lead at Air Products and Chemicals (Allentown, Pa.), notes that people realize that materials' mechanical properties are more important than first thought, and that there's a penalty whenever the dielectric constant is lowered. "You cannot have a k of 1.0 with SiO₂'s mechanical properties. We've learned from FSG. While at first it seemed that FSG might be a one-generation fix, it has been implemented for both 180 and 130 nm nodes. OSG is being used in limited production at 130 nm, but full OSG implementation will be likely at 90 nm."

The industry avoids processing scheme changes — it wants drop-in replacements. "Users say they have a threshold minimum requirement for material properties — in particular mechanical properties that everybody seems to target at a certain dielectric constant — to be able to fit new materials into traditional process schemes," O'Neill said. "There are also interfacial issues, adhesion issues, etc., but on the mechanical side there'll be issues with CMP, packaging, etc." The delay in introducing OSG materials has given everyone time to improve properties and processes for low k — to deposit the film, improve precursor chemistry, and optimize the k and mechanical strength trade-off by slightly raising the k value (the original k=2.7, 2.8 generation is now 3.0-3.2). At 65 nm, instead of implementing porous materials, perhaps suppliers will continue improving the material. Where at 90 nm there might be a dense OSG with k=3.2, for 65 nm there could be a dense OSG of k~2.8. The move to k<2.7 materials will probably occur at 45 nm.

Peter Loewenhardt, dual damascene technical director at Lam Research (Fremont, Calif.), perceives yield as the focus for the first-generation low-k (FSG) dual-damascene production ramp at 130 nm. "From an etch perspective, steps once considered straightforward, such as damascene trench and barrier etch, have become key influencers of yield. The large exposed area — 40-60% — at the trench level makes the step more sensitive to defectivity, which can be addressed by running a confined plasma and in situ cleans to minimize polymer deposition on the chamber walls. Achieving a vertical profile with no copper damage for barrier etch is key to the success of subsequent steps."

Looking forward to the 90 and 65 nm nodes, customers are keeping multiple low-k films on their roadmaps, including FSG, OSG and organic films. As a result, etch tools will need to provide significant process flexibility to meet the wide range of possible integration schemes.