How Does Wafer Layout Affect Yield?

The layout of die is typically designed to maximize the number of gross die per wafer and, therefore, productivity. However, a number of factors, especially the exposure and test times of wafer steppers and probers, respectively, mean that this strategy of die placement may not lead to the highest yields. Out of a benchmark study of 16 integrated device manufacturers, WaferYield Inc. (Santa Clara, Calif.) devised a better approach to wafer layout that optimizes the number of yielding die as well as production throughput. This approach can lead to a 6% increase in the number of yielding die.

"We have found that two different placement strategies that have the same number of gross die on the wafer can have a stepper throughput that differs by up to 18%," said Ron Sigura, WaferYield's president and CEO. He explained that, on average, 7% of stepper or scanner throughput is used to produce only 1% of the die that are typically on the wafer edge and the least likely to yield. The company's WAMA (Wafer Mapping) field/die placement tools perform global optimization — taking into account yield, stepper and tester productivity, cost and return on investment — and find the placement strategy that best optimizes all parameters. "This balanced placement may not maximize the number of gross die per wafer, but it will maximize overall yield and productivity," Sigura said.

This benchmark study revealed that about half the companies use manual placement methods while the other half use in-house software that maximizes the number of gross die on the wafer. In a few cases, die were placed on the wafer using a strategy that minimizes the total number of reticle fields. This approach, however, assumes that all reticle fields have the same number of mask levels. This is no longer valid today because some of the reticle fields contain only the CMP layers (three to seven mask layers), while others contain a full mask set (16-30 masks), according to Eitan Cadouri, WaferYield's chairman and chief technical officer. Printing CMP fields takes significantly less time than printing other fields. In addition, Cadouri said that all fields do not use the same flashing time. "In some cases, blading is being used, and blading a reticle field takes significantly more time than a regular field." Simulating stepper processing time for different placements that produce the same number of die on the wafer revealed that stepper processing time varies between 4 and 18%.

In stepper exposure, some of the productivity gain comes from reevaluating the exposure of chips at the wafer edge. For instance, if the stepper field is exposing four die per exposure around the wafer edges, the alignment process takes longer, and perhaps one or two of the die will not yield at all because only part of the reticle array is inside the wafer.

In the probing arena, users typically place die on the wafer and then generate a probe map for that array. Instead, WAMA software implements the placement that will take prober operating constraints into consideration. On average, the company claims it can improve prober throughput by 5-15% using this approach.

Perhaps best of all, this wafer mapping approach does not require any changes to the manufacturing process. It supports steppers and scanners from all the major manufacturers, and helps to integrate design, manufacturing, assembly and testing operations.

For additional information on yield management, go to www.semiconductor.net/yield.