Controlling Nanotopography to Increase SOI Yields

Now that heavy hitters like IBM, Intel and AMD are implementing silicon-on-insulator (SOI) technology into mainstream production lines, production metrology tools are moving in as well. A key ingredient in more widespread use of SOI is increasing wafer yields and driving down wafer production cost. With severe scaling, any variations in wafer flatness or nanotopography can impact yields and device performance.

Just to zero in on what is meant by nanotopography, consider that, in a 130 nm technology node SOI device with a fully depleted design, the silicon active area is only 20-33 nm thick, on top of a buried oxide (BOX) that is 49-81 nm thick (in partially depleted SOI, the active area is ~5× thicker). To meet a 95% device yield, the tolerance on each of these thicknesses is ±5% —±1.0 nm on a 20 nm film and 49 ±2.45 nm on the BOX. Amazingly, manufacturable solutions exist today for meeting these specifications.

Of course, the specs get tighter at the 90 nm node. No known manufacturable solutions exist today for fully depleted designs, where the active area can be 11 nm thick (must be controlled within 6 Å) and the BOX is 28 nm thick (controlled within 14 Å). Without this control, gigahertz microprocessors will not operate as designed. For 300 mm wafers, nanotopography control at the wafer edge (2-3 mm exclusion, going to 1 mm) is mandatory. "The main reason people are going to 300 mm is to reduce costs, so without high-yielding die on the periphery, that cost reduction can be lost," said Peter Nunan of KLA-Tencor (San Jose).

Combining wafer shape, thickness, flatness and nanotopography metrology in a single scan, the NP1 system targets SOI and bare wafer monitoring in-line, at multiple points during wafer and device manufacturing. (Source: KLA-Tencor)

Starting silicon parameters of interest include wafer shape, thickness, flatness and nanotopography metrology for both SOI and bulk silicon wafers. Something that is unique to SOI is reflectivity off the BOX layer, which makes thickness measurement very difficult by typical scatterometry methods.

KLA-Tencor (San Jose) developed the NanoPro NP1 tool as a one-stop solution for wafer geometry and nanotopography measurement (Figure) for SOI and bulk silicon wafers. The system uses grazing incidence angle measurement and proprietary interferometry methods to solve the reflectivity challenges. The tool measures thickness from initial grinding and etching stages of wafer manufacturing to final double-sided polished characteristics. In IC manufacturing, the technology increases stepper throughput by replacing wafer flatness measurements that today are made site-by-site on the stepper.

Several wafer manufacturers are using the NP1 to screen starting silicon wafer quality, "so that we use only those wafers capable of building good SOI," Maleville said. "We are also able to link final SOI wafer specifications at the customer with incoming wafer specs, to ensure wafer quality in terms of nanotopography and flatness." In the NP1 system, advanced surface nanotopography filtering and spatial sampling resolution algorithms allow precise measurement with no compromise of edge roll-off data for bonding yield. In lithography, focus window is defined by the NT specs that can be met and maintained across 200 or 300 mm wafers. Beyond litho cells, the tool is also applied in chemical mechanical planarization (CMP) processes to detect minute topographical differences with much higher precision than previous technologies.

The NP1 system also helps detect a variety of defects in SOI wafers, including hydrofluoric acid (HF) defects, threading dislocations, particles, voids and stacking faults. HF defects (can be decorated by HF) are the most serious because they have a yield-killing ratio approaching 1.0. These are non-silicon-containing particles that can become silicided defects. Maleville said that trapped particles can also generate voids in the SOI wafer. Particles become trapped between the device and the two wafers to be bonded, severely affecting edge bonding quality. He added that the new technology has allowed his company to improve the edge bonding process and drive SOI edge exclusion to 1.5 mm on a 300 mm wafer.

For additional information on yield management, go to www.semiconductor.net/yield.