The Look of Low-k for 90 nm and SoC

The industry is still searching for the "perfect" material with a low dielectric constant (low-k dielectric) to minimize capacitance that leads to signal time delays and cross-talk between circuits. As we've reported in past issues, both chemical vapor deposition (CVD) and spin-on low-k solutions have been fielded by a variety of companies, and several solutions are capable of meeting the k<2.5 requirement of the 90 nm node. Of course, the major challenge is not necessarily producing a material with a low dielectric constant, but integrating that material into a real-world copper/dual-damascene interconnect process and, for system-on-a-chip (SoC) applications, integration with memory.

At the recent International Electron Devices Meeting (IEDM), researchers from TSMC (Hsinchu, Taiwan) said that "major process modifications" were required to overcome the integration challenges of "porous and mechanically weak" low-k dielectrics. They noted challenges associated with patterning, photoresist poisoning, chemical mechanical planarization (CMP) and damage, pattern density sensitivity, thermal stability and reliability.

TSMC investigated a porous SiOC:H film that was deposited by PECVD using alkyl-silane, carbon and oxygen-containing precursors, which did not require post-annealing. The dielectric constant was measured to be 2.5, the leakage current density 3.0 × 10^-9/cm², and the breakdown field 6.5 MV/cm. The film had a slight tensile stress of 2 × 10⁸ to 7 × 10⁸ Dyne/cm², and a hardness of 0.5~0.9 GPa. The film density was measured to be about 1.0~1.2 g/cm³. The average pore size and porosity were ~6 Å and ~18%, respectively.

TSMC has demonstrated eight levels of copper interconnects integrated with a SiOC low-k dielectric (k=2.6 after integration). (Source: TSMC)

At IEDM, Toshiba (Tokyo) also reported on low-k integration efforts, noting that "low-k dielectric introduction to LSI makes device integration complicated because of its weak mechanical and active chemical property." Their view of integration was SoC-oriented, so front-end devices, memory and packaging were included in the study.

An interesting observation by Toshiba is that, for SoC, the thickness of the first level of metal (metal 1) is critical in that it must be evaluated not only in terms of electromigration resistance, but also DRAM pause time distribution, since bit lines of embedded DRAM are formed with metal 1. A thicker metal 1 is preferred from a current density point of view. On the other hand, DRAM pause time characteristics requested thinner metal 1 from a bit-line coupling capacitance point of view. To overcome these contrary demands, improvements of electromigration durability and an increase of DRAM cell capacitance were performed by "brushing up" process conditions. Metal 1 thickness was defined as 200 nm to satisfy both of these demands.

Another consideration when integrating low-k dielectrics into SoC devices is the metal fuse needed for embedded DRAM/ SRAM redundancy (fuses need to be located in the top copper layer). To prevent damage to neighboring fuse line and under-layer low-k dielectrics, laser blow conditions needed to be optimized in terms of beam energy and spot size.

Interestingly, Toshiba was fairly conservative when it came to the low-k dielectrics used, preferring SiOC and FSG. Six copper metal layers that included all types of interconnect were fabricated on transistors and memories. PE-SiOC (k=2.9) was used for intermediate layers and PE-FSG (k=3.4) was used for semi-global layers. PE-SiCN (k=5.0) was also introduced as local, intermediate and semi-global stopping layers on metal. A PE-SiO₂ capping layer was adopted on PE-SiOC to prevent scratch defects during copper CMP.

Samsung (Seoul, Korea), also reporting on SoC integration issues, was equally conservative. Although aggressive in other areas, including the use of high-k gate dielectrics and silicon-on-insulator, the low-k dielectric and the etch-stop layer used were SiOC (k=2.9) and SiC (k=5.0), respectively.

For additional information on wafer processing, go to www.semiconductor.net/wafer.