Thermal Processing Looks to Speed, Lower Temperatures

The ability of a silicon surface to form a SiO₂ passivation layer has been semiconductor technology's enabler. As device architectures progress and exotic materials are introduced, oxidation has grown increasingly more complex, and thermal budgets have acquired unparalleled importance. As devices continue to scale, the industry is rapidly finding out that industry roadmaps may be overly conservative (Table).

Brian Haas, general manager of the RTP Product Group at Applied Materials (Santa Clara, Calif.), divides rapid thermal processing into two main applications. "The first is anneal — silicides and ultrashallow junction (USJ) anneals. Then there's oxidation. Today's production requirements are driven by 130 nm needs, with spike anneal for ultrashallow junction. The main theme is production readiness. That's particularly true for 300 mm, because it requires a robust system and the management of a more difficult substrate."

"One must begin with RTA vs. furnace anneals," said Chris Werkhoven, vice president of strategic marketing at ASM International (Phoenix). "It was said that 300 mm marked the end of the furnace era — the same was predicted about 200 mm. Although there's a move toward single-wafer systems, particularly RTA, there's a strong base of furnace processes required for 300 mm. Whether at the front or the back end, furnace-based anneals haven't disappeared."

The critical gate overlap lateral junction depth and box-like profile equivalent electrically active dopant concentration levels have been added to the roadmap table.

"Key elements in USJ formation are junction depth and sheet resistance, and process manufacturability and repeatability," said Brian Desmarais, director of ion implant and RTP marketing for Axcelis Technologies (Beverly, Mass.). "More aggressive junctions demand low thermal budgets, which require processing at a high ramp rate with a minimum of peak temperature overshoot. A steep thermal profile gives the best junction characteristics by limiting diffusion but challenges one's ability to deliver the process uniformity and repeatability on a consistent basis."

Applied's Haas views USJ (the spike anneal) as a major challenge in RTP anneals. "The spike's width is defined as the rise in temperature, reaching the peak, and coming back down. Within 50°C of that peak, the time spent within that range — the spike's cone top — is the spike width, which must be under 2 sec to enable USJ for 130 nm."

The primary challenge is production worthiness, measured by within-wafer uniformity and wafer-to-wafer repeatability, to get product to yield at the wafer's edge, especially as device geometries shrink for extendability to next-generation devices, where an even shallower junction must be ensured. "Today's spike width also meets 90 nm requirements; however, it requires optimization of implant conditions," Haas said. "Properly tuned implant conditions, coupled with lamp-based RTP spike anneal, enable not just today's 130 nm production but also tomorrow's 90 nm production." Beyond 90 nm, traditional lamp-based technology may allow early pilot R&D for 65 nm, but will be inadequate when the industry moves into 65 nm production. Much depends on what is learned about specialized implant optimization. These are "cocktail" implants that involve not just boron or BF₂, but also carbon or fluorine.

"The technology requires an extremely short energy pulse," Haas said. "It must only heat the wafer's device (top) layer, without relying on substrate heating. Today, the entire wafer is heated, heating in turn the devices on it, resulting in diffusion at the top few microns. But with USJ for future devices, architecture changes such as solid-phase epitaxy (SPE) and raised source/ drain could be needed. Unless a different structure is used, it might be necessary to go to something focused on dopant activation without diffusion at the transistor's device layer, without heating up and cooling the entire substrate — the whole wafer cannot be heated and cooled that quickly."

Production readiness is the challenge for USJ. "Exceptional ambient control must be maintained, because even in USJ there's sensitivity to trace amounts of atmospheric contaminants — oxygen, water, etc.," Haas said. "In a production environment, flexibility to handle wafer variations (different emissivities and product types), and lot size variations is essential."

But how to handle multiple wafer types' emissivities, yet simplify the set-up? The focus must be on manufacturing robustness, ambient control and versatility. This requires flexible and proven recipes, built-in intelligence, closed-loop control and a well-controlled ambient environment inside the process chamber that guarantees low impurity levels — below 1 ppm of a contaminant such as oxygen or water vapor.

Another anneal application is low-temperature silicide formation for contact metalization. Although CoSi is the mainstay at 130 and 90 nm, the industry is transitioning to NiSi at 65 nm. NiSi enables reduced junction silicon consumption, lower sheet resistance, and formation without agglomeration at lower temperatures compared with CoSi. Because of its lower transformation temperature, NiSi requires low-temperature control. RTP's challenge is that temperature is typically measured using optical pyrometry. The infrared signal from a wafer at low temperature is weak compared with that from one at high temperature. The signal-to-noise ratio worsens with low-temperature processes — it is difficult to measure low wafer temperature and control it with a lamp-based system. Pyrometry electronics and optics must be further optimized to increase detection sensitivity at low temperatures, without compromising on high temperature and dynamic control. Multipoint temperature control is necessary to eliminate within-wafer variability. Also, production requirements for the newest RTP technologies dictate that varying emissivities and wafer types yield transparent process results down to 300°C.

Diffusionless dopant activation methods and their limitations based on boron electrical activation limit and high-k gate dielectric material thermal stability.

The formation of low-sheet-resistance USJ and low-temperature silicide such as NiSi are problems for next-generation devices, said Woo Sik Yoo, president of WaferMasters (San Jose). "To electrically activate implanted species without moving the junction, wafers must be heated and cooled in well under a second. Given that USJ formation is successful, the junction can move during the subsequent thermal cycle such as silicide formation, for example. To prevent junction movement after USJ formation, the temperature for subsequent process steps must be kept <600°C."

New annealing techniques and systems are needed for USJ formation. The temperature ramp-up and ramp-down rate of tungsten halogen lamp-based "spike anneal" is too slow (~1 sec), sheet resistance is too high and the junction moves during annealing. "Laser annealing provides a fast temperature ramp-up and down (<100 nsec), but repeatability and process integration issues are concerns. An alternative technique is arc lamp-based flash anneal, which provides a short thermal cycle (<100 msec) providing acceptable sheet resistance without moving junctions," Yoo said.

"The last challenge is oxidation," Applied's Haas said. "There's a range of oxidation steps, and some are well-suited for RTP because of thermal budget issues. Those steps are the STI liner and the sacrificial oxide (sac oxide). The challenge for STI liner — for the whole STI module, which incorporates both the liner and the sac oxide — is stress reduction. As geometries shrink, stress dislocations induced in devices become troublesome."

The STI liner, whether grown in a furnace or an RTP chamber, can be prone to stress. This film is typically grown in a slow-ramp furnace, resulting in film non-conformality. "In the trench, there's the sidewall and the bottom wall, a top corner at the sidewall's top, and a bottom corner where the bottom wall meets the sidewall," Haas said. "The corners must be well-rounded or else dislocations occur. For good conformality, the sidewall must be as thick as the bottom wall. Otherwise, the STI narrows with liner oxide growth, worsening the aspect ratio. If the liner causes the STI to neck down too much, it makes that depth that much more difficult to fill with a quicker deposited oxide, such as HDP-CVD — and this propagates upstream in the process flow."

To address this issue, a conformal liner and the technology to grow it are required. The traditional, slower oxidation must be replaced with a more aggressive oxidation: in situ steam generation (ISSG), which occurs above 5 Torr pressure. ISSG uses hydrogen and oxygen introduced together, unreacted, into the chamber. The reactants remain as free-species O₂ and H₂ until they reach the wafer's surface, where heat induces a local reaction. H₂ and O₂ react to form steam and oxygen radicals. The unstable oxygen radicals promote more aggressive oxidation of the wafer's top surface than atmospheric dry or steam oxidation, resulting in a higher-quality, more conformal oxide.

These aggressive radicals enable good STI liner corner rounding. They tend to be insensitive to the crystallographic plane, whether on the sidewall or the bottom wall, and predisposed to grow the oxide equally for both walls, rather than being preferential to the sidewall and not to the bottom wall, as with standard dry or steam oxidation. They also tend to be insensitive to the dopant level in the device. This avoids later HDP-CVD problems caused by necking down the trench.

A film previously considered not as critical as the STI liner for stress management is the sac oxide. "But we now understand how its growth impacts the device," Haas said. "It's been determined that, while ramping up to grow that oxide, oxygen which was trapped within the trench's HDP-CVD fill diffuses and migrates towards the shallow trench walls. As it diffuses, it further oxidizes the STI liner oxide as it continues growing." Particularly at 90 nm and below, the volume expansion of the STI liner during traditional slow-ramp furnace oxidation induces stress. Here is where the radical oxidation, particularly when done in a single-wafer, RTP-style chamber, is helpful. In RTP, the rapid ramp-to-soak temperature prevents diffusion of oxygen from the trench to the trench walls and, hence, reoxidation of the STI liner. The quick ramp-up and ramp-down blocks that diffusion opportunity.

However, there is a high-temperature soak period needed to grow the sac oxide, and fast oxidation is needed here because longer time at temperature results in more diffusion of oxygen. "It's possible to grow that film quickly enough for the sac oxide by running ISSG in an RTP chamber," Haas said.

ASM's Werkhoven believes furnaces offer high reliability and low cost per wafer. "Compared to single-wafer processes, it's a mature technology. Scaling to 300 mm has simplified things from a process viewpoint — the silicon-to-quartz surface proportion has improved. This makes <1% uniformities achievable in batches of 150 wafers." Undeniably, initial development increasingly takes place on single-wafer machines — development times are shorter. A single-wafer machine is simpler to handle when developing something new, while a furnace has many wafers that need to be within specification, and more care has to be taken to avoid particles. Single-wafer machines excel there, but industry pressure to port single-wafer processes with low throughput to batch machines is high — also with ALCVD.

At 90 nm and certainly at 65 nm and beyond, transistor manufacturing technology will change. The use of SiGe — in HBTs and now in CMOS for strained silicon, elevated source and drain, and possibly deposited junctions — will not stop. Beyond germanium, there is now polycrystalline high-k HfO₂ gate dielectrics, where amorphous oxide once dominated, while metal electrodes will ultimately replace polycrystalline poly-Si.

Most of the new thermal technologies will first be used in planar CMOS and, undoubtedly, from single-gate, signs point to double-gate structures. "Vertical geometries and structures like wrap-around gates may be entertained," Werkhoven said. "The number of layer steps will substantially increase. CDs will be more dependent on self-aligned technologies and less on stepper resolution. This requires tight requirements for thin-film deposition in areas like step coverage and thickness uniformity. If a layer isn't at least 1% uniform or has almost perfect step coverage, it'll never qualify."

Except for early phases — as during substrate definitions such as SOI and strained silicon — thermal processing is required to go to lower temperatures. With shallow junctions already present, whether implanted and spike annealed or deposited, manufacturers do not want dopants to drift. Future devices will require temperature ceilings of 700°C or less. With new chemistries included in ALCVD or similar processes, these temperatures will certainly become achievable.

Axcelis' Desmarais bets on a hybrid system. "Ours is an RTP system, but like a furnace it's at a fixed temperature, and the temperature source doesn't change," he said. "The power input isn't cycled on and off to heat the wafer. The wafer's quickly taken from a relatively cool environment, mechanically moved into the processing environment, then brought back to the cool region. Because of a stable isothermal environment and a model-based temperature control, we know when it'll reach its peak temperature on the spike anneal before getting there. Thus, when it hits peak temperature, the wafer's already moving down into the cool region, providing the abrupt thermal profile within the thermal budget, while providing world-class uniformity and repeatability."

Users want lower thermal budget processes compatible with existing installed tools and, going into new materials, things like high-k dielectrics and new types of contacts for back-end applications, said Tony Dip, process manager for thermal processing at Tokyo Electron (Austin, Texas). "Size complicates thermal processing — larger wafers are harder to process. Managing 300 mm production lines requires economical, more intelligent tools. A thermal processing system is already well provided with sensors, and there's sufficient monitoring built in — you can tell when the exhaust needs cleaning, track temperature drift, and even recover from common heater drifts or failures."

Dip added that here is where intelligence comes in. "We'll have things like APC. You'll know in real time if the tool is drifting, and which variable must be brought into line to get the film target back in line within the process. This isn't necessarily a hardware change. What it requires is hardware/software coupling and implementing real-time correction."

From a USJ annealing perspective, as devices scale beyond 90 nm, the industry will move to diffusionless activation, said Sandeep Mehta, director of strategic applications at Varian Semiconductor Equipment Associates (VSEA, Gloucester, Mass.). "Ion implantation and dopant activation processes will decouple. Therefore, the as-implanted profile becomes the final dopant profile (because the activation process isn't supposed to perturb it). Furthermore, from an ion implantation standpoint, the precision with which dopants are placed in the transistor becomes paramount. This requires precise control of the implanter's energy, dose and angle of incidence. There are two choices for diffusionless activation — the high-temperature activation process or the low-temperature one being pursued."

Mehta believes that, with diffusionless profile, the decoupling between the ion implantation process and activation mandates precise control of dopant placement, requiring a single-wafer ion implanter with parallel beam (Figure). "Not only for source/drain extensions (SDE), but in the rest of device processing as well. For example, well doping and halo doping all require precision doping. The batch tools suffer from a lack of angle control due to limitations in their inherent design, and therefore cannot deliver the level of precision required for advanced technology nodes."

For <130 nm devices, effects of the vertical device structure on the ion implant process, such as shadowing and pattern shift, become critical. To avoid these issues, self-aligned SDE doping is carried out at a tilt angle of 0°. Any error in the beam steering angle will result in loss of dose at the gate-SDE edge and lead to unacceptable pattern shift. Also, beam blow-up at low energies, typical of SDE doping with batch tools, further exacerbates the dose loss at the gate-SDE edge due to shadowing. To overcome these issues, one requires a parallel beam and, simultaneously, good control of angle of incidence, to deliver the dopant with precision, exactly where it is required. This favors single-wafer tools.

Most non-contact pyrometers used in RTP are sensitive to temperature control above 650°C. For SPE, control stringency will be more relaxed than for a spike or flash anneal at high temperatures. The heating mechanism will change because SPE is in temperatures from 500°C to the low 600s. Using lamp heating and pyrometers for low silicide processing is difficult. Those looking at low-temperature furnaces must go to things like resistive heating or non-optical temperature sensors.