Packaging Combinations Create Optically Enabled Silicon

Silicon allows superb high-density, low-cost active electronics, but poor optical detectors and emitters. GaAs, on the other hand, allows great optical detectors and emitters, but only low-density, expensive active electronics. The best of both technologies is possible by combining the active silicon with GaAs detector and emitter arrays, integrated by the packaging.

Xanoptix (Merrimack, N.H.) has combined more than seven leading-edge packaging technologies to allow any silicon chips to be optically enabled. This effort took more than 12 years of development, and has resulted in a suite of technologies that can be applied to any silicon chip by adding a few design features, said Thomas Faska, vice president of engineering.

Xanoptix builds small arrays of optical detectors and vertical-cavity, surface-emitting lasers (VCSELs) in GaAs. Depending on the application, these are in 1 × 12 to 3 × 12 arrays. Through vias, with a pitch as tight as 10 µm where needed, are fabricated in the GaAs chips and metalized to allow electrical interconnect to the back side. The top surface is available for the optical interface. Though fabricated on Xanoptix's captive line, this process also has been licensed to other foundries.

The GaAs chips are attached to the center of the active silicon chip in a process described by John Trezza, president and CTO, as a "proprietary fusion process."

On the silicon chip, which can be manufactured on any standard CMOS line, are the drivers and receivers with the necessary processing circuitry. Pads are designed for both attach of the GaAs chips and multiple peripheral rows for the silicon I/O. The silicon wafer is metalized to support the GaAs attach and either flip chip of the silicon or conventional wire bonding.

According to Faska, the pad I/O and driver and receiver circuitry can be added to any silicon chip, so, in principle, any silicon device could be optically enabled. He noted that the I/O bottleneck between processors and memory arrays might be broken by optical interconnects.

Assembly of the GaAs detector and emitter array chips to the active silicon is done at the wafer level to reduce costs. Alignment can be within 1 µm using conventional assembly equipment.

1. Silicon hybrid chip with a GaAs detector and emitter arrays. (Source: Xanoptix)

After attach of the hybrid silicon chip to the substrate, with the top surface of the GaAs arrays facing out through the hole, the GaAs and silicon chips are underfilled to provide environmental protection. A high-performance heat sink, with X-Y holes to facilitate heat transfer, is attached to the backside of the silicon chip.

The final assembly step is to attach an MT-style ferrule socket to the package. This is an industry-standard connector for an n × 12 array of multimode fibers. The socket is precision-aligned to the package, which is aligned to the silicon. The silicon is then aligned to the GaAs detectors and emitters.

2. Completed transceiver modules. (Source: Xanoptix)

The only unusual technology in this portfolio is through vias in the GaAs wafer to facilitate optical transmission from the top of the GaAs substrate and electrical connections through the bottom.

Applicable to any generic silicon device, this combination of seven packaging technologies — low-cost wafer bumping, chip attach to the active silicon, wafer-scale assembly, flip-chip attach to a flex substrate, an area array BGA socket, high-efficiency heat sink and alignment of the optical fiber socket to the package — enables optical interfacing. As Faska said, "We excel at bringing all the various technologies together." Indeed.

For additional information on semiconductor packaging, go to www.semiconductor.net/assembly