Symposium Investigates Reliability Near the Red Brick Wall

Perhaps nobody is more keenly aware of the reliability issues at technology's leading edge than the speakers and chairs of the International Reliability Physics Symposium (IRPS), which IEEE first organized more than four decades ago. With its latest meeting to be held this month in Dallas (March 30 through April 4), the conference is sure to uncover new reliability challenges as the industry approaches the red brick wall, where continued scaling alone will not produce reliable devices that perform acceptably.

This year, there will be particular emphasis on device breakdown behavior with continued scaling of gate oxides in MOSFETs, the characterization of high-k gate dielectrics, and the causes of electrical failures in multilevel copper interconnects with low-k insulating dielectric. The event will kick off with keynote addresses by Mark Bohr, senior fellow at Intel (Santa Clara, Calif.); and Shang-yi Chiang, senior vice president of TSMC (Hsinchu, Taiwan).

According to the laws of physics and current transistor design, the limit of scaling for traditional oxides (SiO₂ and nitrided oxides) is somewhere around 12-15 Å. Near this limit, the existing principles of dielectric breakdown no longer hold. Thin gate dielectrics no longer undergo well-defined hard breakdowns, which cause catastrophic device failure. Instead, they demonstrate soft failures, where leakage currents through the dielectric increase less dramatically and oxides still maintain some insulating properties and functionality. At the IRPS, researchers from IBM (Yorktown Heights, N.Y.), Agere Systems (Berkeley Heights, N.J.) and STMicroelectronics (Crolles, France) will provide insight into soft breakdown characteristics upon negative bias temperature stress testing, modeling and experimentation.

System-on-a-chip devices typically feature gate oxides of different thickness to allow transistor operation at different supply voltages. Researchers from LSI Logic (Gresham, Ore.) will describe a 90 nm technology with quadruple gate oxides (16, 28, 50 and 64 Å), for operation at 1.0, 1.2, 2.5 and 3.3 V. The group found that, rather than depositing the gate dielectric by conventional means, a pre-gate nitrogen implant can provide better interface quality and integrity as well as lower leakage current.

In terms of alternative gate dielectrics, reliability has been the key impediment to adoption. Researchers from IMEC (Leuven, Belgium) have determined that threshold voltage stability, a key challenge for alternative dielectric systems, is caused by charging and discharging of pre-existing defects in the HfO₂ layer. This charging instability complicates the reliability characterization of these new materials and must be better understood. Another IMEC paper addresses dielectric breakdown in alumina and zirconium oxide stacks (SiO₂/Al₂O₃ and SiO₂/ZrO₂), which takes place through competitive degradation of the two dielectric layers. Therefore, the conduction mechanism through both layers is needed to accurately characterize behavior.

Electromigration (EM) failures in dual-damascene copper interconnects can be caused by the fabrication process as well as the geometry of the interconnects. Researchers from IBM (Essex Junction, Vt.) will show how the line/via layout, fabrication process and liner robustness affect EM behavior. Researchers from Infineon Technologies (Munich, Germany) determined that temperature coefficient of resistance (TCR) measurements can provide an early reliability monitor for stress voids in copper. The TCR monitor can be useful in process development, qualification and wafer-level monitoring.

In an investigation of EM and stress voiding (SV), a group from ALTIS Semiconductors (Essonnes, France) and Infineon Technologies performed comprehensive studies on SiN dielectric capping layers commonly used to seal copper lines. They discovered that there is a trade-off between EM and SV performance depending on the pretreatment. An aggressive pretreatment improved the Cu/SiN interface properties and EM lifetimes. However, the preclean can also cause microstructural damage to the bulk copper, making it more susceptible to stress voiding.

One alternative to tantalum-based copper barriers is TiSiN by CVD. Researchers from Novellus Systems (San Jose) and International SEMATECH (Austin, Texas) were able to improve the adhesion between barrier and dielectric using an alternative preclean method that improves the reliability margin for these CVD barriers.

Though a variety of low-k dielectrics continue to be pursued, it appears that different materials may at least share some failure mechanisms. Researchers from Texas Instruments (Dallas) compared the leakage, breakdown and time-dependent dielectric breakdown (TDDB) of fluorinated oxides, carbon-doped oxides and porous carbon-doped oxides. They will report that breakdown strength and TDDB values tend to degrade with increased porosity, but the failure kinetics are similar. Meanwhile, a group from AMD (Sunnyvale, Calif.) will characterize key electromigration parameters as a function of line length for both low-k and SiO₂-based materials. The low-k materials demonstrated lower mean time to failure for a given length of copper wire.

In addition to the sessions on transistor and interconnect reliability, the IRPS also covers the reliability characteristics of various devices, including compound semiconductors and memory devices, device and wafer-level testing methodologies, packaging reliability and failure analysis. The IEEE also added a new presentation this year, "A Reliability Year in Review," which will bring attendants up to speed on the latest developments in reliability physics. For more information, see www.irps.org.