Low-k Dielectrics Drive Metal-Barrier-Free Copper Interconnects

Because dielectric barriers have proven effective at sealing the tops of copper lines, one might ask whether they would be a suitable replacement for the metal barrier that surrounds the copper vias and lines. TSMC (Hsinchu, Taiwan) explored this possibility in a presentation given at the recent IEEE IEDM conference. The researchers proposed a metal-barrier-free copper interconnect scheme for 90/65 nm back-end-of-line (BEOL) technology that demonstrated compatibility with low-k CVD OSG films.

Though tantalum-based ALD barriers are expected to succeed PVD tantalum-based barriers, TSMC notes challenges of ALD film purity and possible metal precursor penetration into porous low-k films. For the existing low-k OSG films (k~2.5), TSMC tested the reliability of copper interconnects when TaN barrier was replaced with three different PECVD silicon carbide-based barriers, SiC (k=3.9), SiCN (k=5.0) and SiCO (k=4.2). The dielectric barriers afforded an 8% decrease in RC delay, a 36% decrease in via resistance, three orders of magnitude difference in line/line leakage at 200°C and dramatically enhanced time-dependent dielectric breakdown (TDDB). Ring oscillator delay of 90 nm CMOS devices was 15% faster relative to the same structure with TaN barrier.

The copper dual-damascene process used no trench etch stop layer, and the dielectric etch stop (40 nm) at the via bottom was etched during the underlying barrier open etch. A key advantage to dielectric barriers is the less dramatic increase in RC delay with increasing thickness relative to metal barriers. For this reason, a SiC-based replacement of metal barrier can deliver incremental RC improvements without having to integrate ultralow-k dielectrics (k=2.2).

Though all of the 10 nm dielectric barriers successfully mitigated copper drift, SiCN and SiCO showed slightly better barrier characteristics than SiC. The step coverage of SiCN was best, providing 27% coverage of the via bottom in a 4.5 aspect-ratio via, which is acceptable for sub-90 nm devices. Excellent adhesion to both the OSG and copper enabled use of existing CMP processes without peeling.

A 36% improvement in via resistance (0.14 µm via) resulted from direct contact between the copper in the via and underlying line, which likely reduces the chances of copper voiding, leading to electromigration or stress migration failures. The SiC-barrier appeared to reduce the surface field between adjacent copper lines by 28%, resulting in profound reductions in both line/line leakage (l/s=0.12/0.12 µm) and copper TDDB lifetime.