NEC Devises Simple Solution for Stress Migration
Laura Peters, Senior Editor -- Semiconductor International, 2/1/2003
A little titanium may go a long way
toward making more reliable copper interconnects. A group of researchers from NEC Corp. (Kanagawa, Japan) recently found that,
by inserting a thin titanium layer under the traditional Ta/TaN barrier, they
could effectively suppress the formation of stress-induced open failures in
multilayer copper interconnects. The PVD titanium film improved adhesion between
the via and underlying copper line, with an unexpected 25% decrease in via
resistance. NEC reported on its results at IEEE's International Electron Devices Meeting last December.
Stress-induced voids tend to form under vias that are connected to wide copper lines. The voids are caused mainly by copper's larger coefficient of expansion relative to that of the interlevel dielectric.
The NEC researchers fabricated dual-damascene test structures using 0.20 µm vias with 0-30 nm deposited titanium thicknesses followed by ionized PVD Ta/TaN stack, copper seed deposition, copper filling and chemical mechanical planarization (CMP). The testing on 10,000 via chain patterns, under thermal stress of 150°C for 500 hr, revealed that stress migration (SM) void formation is a function of the linewidth of the lower (M1) copper line. Opens occurred if M1 was wider than 1.5 µm. A 30-nm-thick titanium film (8 nm at via bottom) dramatically suppressed void formation, but thinner films (10 nm, ~3 nm on bottom) did little to prevent voids.
NEC examined interfacial properties using electron energy loss spectroscopy (EELS). When no titanium layer was present, copper agglomeration occurred even after a 30 min anneal at 400°C. The EELS spectrum showed that atomic-scale mixing of copper and titanium occurred at the interface during the anneal, which improved SM resistance.
Via resistance improved with increasing titanium thickness and saturated at ~25% reduction. This result was surprising because titanium has higher resistance than copper. The researchers postulated that the decrease was due to better adhesion properties between the titanium and copper and/or titanium's ability to getter impurities. Subsequent electromigration tests (300°C at 3.2 MA/cm2) showed the 30 nm titanium inserted sample had equivalent EM resistance performance to samples without titanium.
In investigating the upper linewidth (M2) dependence on M2 sheet resistance, the researchers found that a 10 µm M2 line had a slightly elevated Rs (8%). Since copper doped with even 1% titanium shows an enormous increase in sheet resistance (200%), the 8% increase indicated that the Ta/TaN barrier prevented titanium mixing with the M2 copper.
For additional information on yield management, go to www.semiconductor.net/yield.