Grating Improves Overlay Metrology
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2003
Lithography is in constant transition. Currently, the major area of development is in subwavelength lithography, where device features considerably smaller than the tool's wavelength are printed. As design rules continue to shrink, so too are lithography process windows, which represent the amount of allowed CD and overlay variation during manufacturing. This affects the focus and exposure latitude within which a desired feature can be printed within specification. Resolution enhancement techniques such as optical proximity correction, phase-shift masks and double exposure are used to enable pattern printing in subwavelength lithography.
To meet the tight process latitude, process measurement and control need to take into account all possible errors. For overlay this means looking at all errors affecting device pattern misplacement. Historically, this has been done through a simple relationship using a plain overlay target — a box-in-box — at the corner of the field, printed by the scanner or stepper to determine through modeling the device overlay. This is no longer a reliable method, particularly because box-in-box targets' feature sizes and dimensions are significantly larger than the device's CDs, and do not correlate with device density.
Traditionally, the key parameters that defined the accuracy and performance of an overlay metrology tool were precision, matching and tool-induced shift, which is the ability to measure the same overlay in reverse orientation. Today, a lithography overlay budget of 40 nm requires 4 nm total precision. At 70 nm design rules, this budget will be 27 nm, requiring 2.7 nm total precision. However, when considering overlay's sources of variation today, feature size pattern placement has now emerged as one of the key parameters defining measurement performance.
The fact that the box-in-box target no longer correlates with that of the device is a major source of pattern placement errors. Another key source is mark fidelity. Artifacts accrue when the box-in-box target is polished, causing mark degradation and resulting in reduced precision and measurement accuracy.
When box-in-box targets go through CMP, they are not in compliance with the fab's basic rules because there has to be a certain feature density per unit area on the wafer. Otherwise, processing results are not optimal, which leads to dishing and erosion. Also, these targets, although boxed, have too much open space in them, violating the constant density required anywhere else in the die.
KLA-Tencor (San Jose) is developing a technology that it expects will handle overlay metrology for the 70 nm node, and possibly beyond. Its grating overlay technology focuses on the reduction of the comprehensive total measurement uncertainty (TMU), a metric that essentially combines traditional overlay tool parameters such as precision and matching with feature size pattern placement and mark fidelity, for one overall definition of measurement uncertainty. At the 70 nm node, more than one-third of the overlay budget will be assigned to mark fidelity, device correlation and tool total precision — clearly an unacceptable situation that requires a new and improved overlay metrology.
KLA's technology uses a grating mark on the reticle, which is more amenable with process and design work. A dense structure that is more compliant with CMP effects, it is therefore less sensitive to CMP and captures the same overlay errors that would affect the device. The grating configuration contains far more edges than a traditional target, which considerably increases the information content. Each of the grating lines can be at the design feature size. If 130 nm processing is measured, each line can be 130 nm. Feature enhancement techniques can be used as part of the target to reflect the exact process conditions. In addition to reducing random errors, this new design makes it possible for the target to also respond, as the device itself, to stepper aberrations and enhanced illumination modes. Because proportion and density are maintained, the lower measurement uncertainty will be achieved at 70 nm, enabling the use of this technology for the next several design nodes.
This technology is being developed to allow overlay control down to 50 nm design rules, with a 30% improvement in the comprehensive TMU from the old box-in-box target method. This should lead to less overlay rework and reduced yield loss.
For additional information on inspection, measurement and test, go to www.semiconductor.net/imt.
