FRAM: The New Contender

Ferroelectric random access memories (FRAMs) just got much more competitive with technologies such as embedded DRAM and flash memory, and cached SRAM. Through a joint project between Ramtron International Corp. (Colorado Springs, Colo.) and Texas Instruments (Dallas), a 64 Mb embedded FRAM technology has been developed and integrated with an advanced 130 nm CMOS logic process, with five-level copper and FSG interconnects.

Advantages over other embedded memory options include FRAM's low cost to manufacture (only two additional masks are required), low power consumption, fast write times and high reliability. FRAMs are also non-volatile and can be packed more tightly than SRAMs. The 64 Mb FRAM device produced has the smallest FRAM cells ever reported, measuring only 0.54 µm². At the 90 nm process node, the generation where TI's first embedded FRAM products are expected to appear, the FRAM cells will be even smaller — a mere 0.35 µm².

"We believe FRAM has the potential to become an ideal non-volatile memory option for a wide range of applications in the 2005 timeframe," said Hans Stork, senior vice president and director of TI's silicon technology development. "This demonstrates that semiconductor materials research coupled with innovative product design can deliver revolutionary advances, and TI believes FRAM can change the product dynamics in embedded memory."

A new embedded FRAM technology uses two additional masks to fabricate a ferroelectric capacitor with iridium electrodes between the contact level and first level of metal. Only the first two of five copper interconnect levels are shown. On the right is a SEM photo of the embedded FRAM module. (Source: Texas Instruments)

The eFRAM module is formed between the contact and M1 levels of a standard logic flow as shown in the Figure. Starting at the contact level, a TiAlN barrier and iridium electrode is deposited, followed by a Pb(Zr_0.3Ti_0.7)O₃ ferroelectric layer deposited by MOCVD. Because the PZT deposition process has a relatively low thermal budget (~600ºC), this flow is compatible with the CMOS front end and can also withstand the temperature requirements for the Cu/FSG backend. Following capacitor stack deposition, a single-mask stack etch removes the Ir/IrO_x top electrode, PZT, iridium bottom electrode and TiAlN diffusion barrier layers. A sidewall AlO_x diffusion barrier layer and etch stop layer is then formed followed by the deposition of a SiO₂ interlayer dielectric. A second mask defines the vias that connect either the top of the capacitor or the contact to M1. Following via planarization, copper metal lines are formed using a single-damascene process and aligned to the eFRAM-level vias. The interconnect process flow then continues in a manner nearly identical to that for the standard copper back end.

Adding FRAM is "potentially a very simple process addition to a logic process because it's only two masks," noted TI's Ted Moise. "You have one mask to form the capacitors and a second mask to form the multilevel vias. That's in comparison to embedded flash or embedded DRAM, both of which take up to six or eight masks beyond the logic process."

The biggest challenge lies in working with unusual materials such as PZT and iridium, which required the development of special deposition and etch technologies. "In order to make these small cells and etch noble metals like iridium, we use a high-temperature etch process that increases the reactivity of these materials so we get steeper capacitor sidewalls," Moise said.

Ramtron's development teams have been working with TI since August 2001, when the companies entered into a multimillion-dollar FRAM licensing and development agreement. In addition to licensing and development fee revenue associated with the partnership, Ramtron has the right to use the jointly developed ferroelectric technology for its own high-density, stand-alone, FRAM memory products.

"What's significant is that in Dallas now we have a path to high density," said Tom Davenport, vice president of Ramtron's FRAM Development Division. "What Ramtron gets out of the work is an ability to use the process for our high-density products." Ramtron's high-density, stand-alone memory products could be available as soon as 2004.

For additional information on emerging technologies, go to www.semiconductor.net/emerging.