Dynamic Random Access Memory (DRAM)

The amazing increase in memory density over the past 20 years has been well documented, with the 1990s seeing an increase from chips with 4 million memory bits (4 Mb) to ones with 256 million (256 Mb). Today, 1 Gb chips are the state-of-the-art, although shrinking the dimensions of 512 Mb chips is still the focus of much research (the number of bits is always a power of 2 because of the binary code input). 4 Gb prototypes have been developed, but their die size is quite large, and the world does not yet seem to need a single chip that can store the data equivalent of 32,000 standard newspaper pages, 1600 still photographs or 64 hours of recorded audio.

In the simplest sense, a memory device must be able to store a bit as a 1 or 0, and it must be able to read or "sense" that state. In the most common type of memory device, the dynamic random access memory (DRAM), the storing of a bit relates directly to a charge on a capacitor. If the capacitor is charged, it's a 1 and if there's no charge, the state is a 0.

A DRAM cell consists of a MOSFET (also referred to as the array-access transistor or transfer device) in series with a storage capacitor. The cells are built in large arrays that are addressed by bit lines and word lines. The word line contacts the gate of the transfer device, and the bit line contacts the source/drain of the transfer device that is not connected to the storage capacitor. Data is written by turning on the transfer device by raising the word line and writing a high or low voltage level onto the storage capacitor via the bit line. Data is stored by turning off the transfer device by lowering the word line, trapping the voltage/charge on the storage capacitor. In industry-standard DRAM, data is conventionally read by precharging the bit line midway between the high and low levels, turning on the transfer device, and sensing the bit line voltage change (the signal voltage) caused by charge sharing between the storage capacitor and the parasitic bit line capacitance.¹

The incredible increase in density has been mostly due to the ability for new lithographic techniques to print smaller and smaller dimensions. But it's also a measure of the industry's ability to continue to find ways to build a capacitor small enough to not take up much room, but still able to store enough charge to be useful. "Pressure to minimize cell size is in conflict with the requirement to maximize the capacitance of the cell for charge storage performance, which puts pressure on memory cell designers to find creative ways through design and materials to meet minimum capacitance requirements while reducing cell size," notes the 2001 ITRS .

One way to do that is to build the capacitor in a deep trench. DRAM cells using trench-storage capacitors are particularly well suited for the integration of vertical transistors, since a portion of the wall of the trench above the storage capacitor is utilized for the channel, while the bit line wiring is formed above the surface of the silicon substrate. The evolution from today's trench cell to a vertical-transistor trench cell is depicted in the Figure.

Evolution from planar to vertical MOSFET cells. (Source: IBM)

For the 0.10 µm generation, a new material with yet higher dielectric constant (relative dielectric constant 20) will be needed. Today, no material has yet been shown to be adequate for this generation, but most companies have been researching barium strontium titanate (BSTO) as the most likely candidate. Although the scaling path for trench capacitors appears to be more certain than that for stacked capacitors, there are many challenges that must be addressed.¹