Hitachi Investigates Wafer-Backside Copper Contamination

Since copper wiring is plated on wafers, copper contamination inevitably forms on wafer backsides, potentially harming device reliability. This is an important concern because copper diffuses very rapidly in silicon under 400°C, the approximate temperature of copper annealing processes. A recent study by Kazuyuki Hozawa, et al., of Hitachi Ltd. (Tokyo) measured the electrical characteristics of MOSFETs fabricated with copper contamination on the wafer backsides. The study determined that backside copper contamination does not affect initial breakdown characteristics, but it can, under certain conditions, decrease time-dependent dielectric breakdown (TDDB) and drastically enhance short-channel effects in sub-100 nm devices. Hitachi reported its results at the IEEE IEDM conference held last month.

The Hitachi researchers used bare silicon wafers with and without silicon dioxide frontside and backside layers and with varying copper concentration. Total reflection X-ray fluorescence was used to measure the copper concentration and depth profiles before and after 400°C annealing for 10, 60 and 120 min. Copper was spin-coated on the wafer backsides at two concentrations, C_low (1.7 × 10¹¹ atoms/cm²) and C_high (4.6 × 10¹³ atoms/cm²).

In the case of bare silicon surfaces and no backside SiO₂ , C_low is slightly lower than copper's solid-solubility limit at 400°C (4.0 × 10¹² atoms/cm²), so it diffuses upon anneal into the bulk silicon. At higher concentrations, the copper precipitates at the backside region (becoming a self-gettering region), and does not readily diffuse into the silicon before 60 min of annealing. The concentration at the top surface tapers off at the solubility limit. With a SiO₂ backside layer and bare silicon frontside, the copper concentration is reduced at the backside SiO₂ /Si interface, presumably resulting from copper's reduced reactivity with oxide.

When the wafer frontside has a thin oxide layer (3 nm) and backside SiO₂, the frontside copper concentration after annealing reached approximately the same level it did with bare silicon. However, with a 6 nm oxide film, the concentration remains under detection limits, even after a 240 min anneal. The researchers deduced that, with thin oxide, almost all copper atoms exist at the SiO₂/Si interface. They propose that copper electrons directly tunnel through thin oxide to the silicon, electrically activating the SiO₂ film, which then allows positively charged copper ions (Cu⁺) to move to the SiO₂/Si interface. But at 6 nm thickness, electrons do not have sufficient energy to tunnel through the SiO₂, so the Cu⁺ is repulsed by the positively charged SiO₂. The copper ions remain near the bottom Si/SiO₂ interface.

The tests on NMOS capacitors showed that copper contamination does not affect device characteristics (flatband voltage threshold, midgap interface state density and time-zero dielectric breakdown), even after 60 min annealing. The copper atoms apparently cannot diffuse into the SiO₂/Si structure (>3 nm). However, copper atoms remain inside the bulk silicon at the SiO₂/Si interface after TDDB. Copper diffuses during the TDDB under negative gate bias, degrading TDDB lifetime due to the electron-field drift effect.

The study further showed that copper atoms can diffuse at impurity regions, affecting MOS transistor characteristics because the copper atoms have a tendency to compensate impurities. Following implantation, copper atoms slightly passivate the electrically active boron and phosphorus, which occurs when implantation dose decreases. Measurements of threshold voltage shift were taken as a function of changing implant dose in short-channel MOS transistors with a channel stop implant and long-channel transistors without channel stop implant. The short-channel effect was dramatically enhanced due to impurity compensation. Based on these results, the researchers recommend careful control of backside copper contamination during processing.

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