Extreme Scaling: 6 nm Gate-Length MOSFETs

One promising option for continued scaling without significant departure from standard device structures is the ultrathin silicon channel MOSFET. With "extreme scaling," IBM researchers have shown that it's possible to fabricate working devices with channels as thin as 4 nm and with gate lengths down to 6 nm.

The International Technology Roadmap for Semiconductors (ITRS) projects that transistors have to be smaller than 9 nm by 2016, and IBM (Yorktown Heights, N.Y.) says it is the first company to make working transistors below that gate length. Although far from ideal, the devices could be turned on and off and had good MOSFET characteristics. The work was reported in December at the International Electron Devices Meeting (IEDM) in San Francisco.

Interestingly, it is of perhaps more interest what the researchers did not do, rather than with they did do. They did not use any radical new technology but instead relied on fairly conventional transistor design and fabrication techniques. For example, they did not use a dual-gate transistor as some have suggested might be required at this level, but a planar single-gate design. Nor did they use a radical lithographic approach but instead stuck with 248 nm technology. Similarly, a highly nitrided gate dielectric and polysilicon gate were used rather than a high-k dielectric/metal gate. The greatest departure from traditional processes was the use of selective epitaxial silicon to form a raised source/drain, and the use of strong halo doping, also known as pocket doping, to minimize short channel effects (SCEs).

"The ability to build working transistors at these dimensions could allow us to put 100 times more transistors into a computer chip than is currently possible," said Randy Isaac, vice president of science and technology at IBM Research. "Moreover, this achievement underscores the fundamental challenges of scaling, namely power density, that must be addressed as silicon is pushed to molecular dimensions."

IBM researchers pushed the limits of scaling using relatively conventional technology, fabricating a 6 nm gate-length planar single-gate transistor with good MOSFET characteristics. The greatest departure from standard processing was the use of selective epitaxial silicon to form the raised source/drain. (Source: IBM)

The researchers fabricated high-performance ring oscillators with ultrathin silicon channels and 26 nm gate lengths, resulting in a CMOS inverter delay of ~10 psec per stage (at V_dd = 1.2). This is the first time such circuits have been built out of transistors with such small gate lengths.

The 6 nm gate-length devices were fabricated with a thinner gate oxide and a stronger halo. Halo doping achieves a lateral nonuniformity by angling in shallow body-type doping from the source and drain ends of the FET with the gate as a mask, creating a "halo" around the source and drain. For short-channel FETs, these halo profiles work to create a higher average doping in the channel than is seen by a longer-channel FET, thus tending to raise the threshold voltage in opposition to SCEs that are lowering it.

The 6 nm devices could clearly be turned off. However, the saturated current at V_dd = -1.5 is degraded to 130 µA/µm. Researchers said the reduced current is likely caused by line-edge roughness; mobility degradation in the channel from phonon and Coulomb scattering; and increased series resistance under the spacer.

For additional information on wafer processing, go to www.semiconductor.net/wafer.