Industry Confronts Sub-100 nm Challenges

The 90 nm node will use 193 nm lithography at critical levels and resolution enhancement techniques (RETs) with 248 nm (Fig. 1). OPC is most widely employed, often combined with other RETs. However, "generically applying OPC to any device is a big challenge and one that we're seeing increasing problems with at the 130 and 90 nm nodes," warned Mike Slessor of KLA-Tencor (San Jose). "Very aggressive OPC may work in the center of the process window, but not at the limits — leading to line bridging or printing of the sub-resolution feature."

"If you apply OPC with complete disregard for the maskwriters, you've increased the complexity beyond what the writers can do at this time," said Atul Sharan of Numerical Technologies (San Jose). He advocates better cooperation among designers, mask manufacturers and device manufacturers. "Engineers have to be constrained on the design so that it will be phase-shiftable and manufacturable."

This 300 mm epi chamber is being used for strained silicon channels, which speeds device operation relative to standard silicon. (Source: ASM International)

For contact hole imaging — a particularly difficult lithography challenge — engineers are investigating several alternatives including e-beam projection lithography (EPL) and chromeless phase lithography (CPL).¹ "CPL is attractive for contact hole imaging because you can get good resolution and depth of focus, while requiring only half the dose. That greatly improves productivity," Carlson said.

Resist inspection with e-beams is limited by line slimming — changes in the critical dimension (CD) when e-beams react with resist. "You can mitigate these effects by preconditioning the resist, finding optimum beam conditions for different resists, or by using optical methods," explained Pete Nunan of KLA-Tencor. Gottscho added, "We're seeing anywhere from 1 to 2 nm of noise induced by CD-SEM metrology, whereas optical CD noise is 0.5 nm." Slessor said that scatterometry has other advantages, such as the ability to measure feature profiles.

1. More complex methods of resolution enhancement are required to stretch performance at any given lithography wavelength. (Source: IMEC)

Slessor said line-edge roughness (LER) and microbridges are important defect modes with 193 nm resists. LER is insidious because it propagates through most aspects of 193 nm process development.

With the widespread use of antireflective coatings (ARCs) and challenges with 193 nm processes, 248 nm bilayer resists are becoming more attractive. "The underlayer is sufficiently absorbing, but it also has the proper etch properties to minimize line-edge roughness while also giving a planarizing effect over varied topography," said Eric Alling of Shipley Co. (Marlborough, Mass.). Shipley's Phillip Rose added that LER has been the most difficult challenge for 193 nm resist development. "Finding the right chemical formulation allows you to optimize for reduced line-edge roughness."

After patterning, maintaining CD uniformity is a challenge. "To compensate for loading effects, we use step-by-step wafer temperature tuning across the wafer, so the profile can be different from trim, mask open and the gate stack," Gottscho said.

Dielectric etching of HAR contacts requires excellent resist-to-substrate selectivity, vertical profiles and prevention of striations in the resist. "On dense arrays, spacing between features can be 100 nm, so you have to maintain the photoresist shape to prevent bridging between lines," said Lam's Jeff Marks. One key to obtaining these results is a short-residence-time, confined plasma, he said. "CD uniformity of 5-6 nm on the contact etch requires better tool repeatability and APC, as well as new ways of matching tool-to-tool condition."

Announcements by IBM, Intel and AMD regarding the use of strained silicon, with or without SOI, have spurred great interest in the two technologies. "Downscaling is still a driver, of course, but not necessarily the only one," said Chris Werkhoven of ASM International (Phoenix). SOI approaches enable reduced leakage currents for low-power applications, while also providing noise and latch-up suppression. Nunan claims that, of all the new material inspection challenges, SOI is surprisingly difficult. "SOI yields are increasingly dependent on nanotopography control at several steps in the process."

"There's a big drive to reduce strained silicon dislocations, which cause yield problems," Werkhoven said. Silicon germanium-based epitaxy can be performed in blanket or selective deposition modes, and there are various methods of grading the SiGe profile, he added.

High-k gate dielectrics and metal gate electrodes theoretically offer performance and scaling advantages over SiON/poly gates, but numerous integration issues must be solved for production. High-k may be implemented with dual-doped poly gates, "to provide orders of magnitude less leakage than SiON dielectrics," said Bob Soave of TEL (Austin, Texas). "But it is unclear if these materials can be directly inserted into a conventional process flow." Metal gate electrodes offer additional performance and scaling advantages by eliminating the poly depletion effect. Alternatively, TEL and other companies are delivering tools that allow SiON delectrics to be extended to the 65 nm node.

"One challenge with high-k gate dielectrics is high sensitivity to the silicon substrate and processing materials that are not yet stable," Gottscho said. The most favored material, hafnium oxide, has recently demonstrated mobility issues. Though high-k dielectrics may use metal organic chemical vapor deposition,² the maturity of the PVD industry lends its use as an R&D system for early material evaluations, said Philip Frausto of Tosoh SMD (Grove City, Ohio).

The high-current ion implant to form shallow source/drain junctions remains the most crucial implantation step. Tool designers struggle to produce high currents at very low energy with acceptable throughput. "Energies can go from 1 keV to 500 eV, and the dose can double, which significantly degrades throughput," said Jay Sorochin of Applied Materials' Ion Implantation Group. Leonard Rubin of Axcelis Technologies (Beverly, Mass.) added, "You need to minimize the ratio of extraction energy to final energy to minimize device leakage caused by energy contamination." Implanters with quad repositioning offer improved process robustness relative to zero-degree implants because key device parameters such as threshold voltage become less sensitive to variations in lithography, etch, deposition and implant, Rubin said. Sorochin claims that high-accuracy, lower-energy-range power supplies and closed-loop control play an important role in junction depth control.

In high-energy (HE) well implants, chaining is becoming a popular approach to throughput enhancement, reducing six to eight implant steps to two (see "Chaining Implants Drastically Improves Productivity"). With 90 nm scaling, it is important to limit device asymmetry effects from well implants, changing the requirement from 7° implants to 2-3°. "Zero-degree implants are undesirable because channeling effects make the final profile shape — and therefore device properties — hypersensitive to minute variations in implant angle," Rubin said. HE implantation processes also use thick photoresist, which causes shadowing. Several device manufacturers are considering single-wafer HE implants, to simultaneously minimize shadowing and channeling, said Applied's Jonathan Pickering.

"With increased packing density, devices also become more susceptible to latch-up, which can be controlled by HE buried layers of boron, either blanket or masked," Rubin said.

Integration and device reliability issues brought low-k dielectric adoption to a halt at the 130 nm node. At the 90 nm node, low-k films (k~2.8) will be used, with many customers leaning toward CVD SiOC dielectrics. Karen Maex of IMEC (Leuven, Belgium) noted the most crucial interconnect issues going forward: "First, we need to get the low-k value in narrow spaces, because that's where it is needed most. Then, the resistivity of the thin copper wires must be better understood. Barrier integrity and low-k integrity are also very important. Finally, reliability issues are paramount, because even with tight process control — at 45 nm spacing, for instance — surface effects and interface effects become dominant, which affects failure modes."

Low-k integration problems include adhesion issues, leading to peeling; and stress build-up in the stack, which leads to creep, stress migration failure or electromigration failure. Stress build-up is an even greater concern for second-generation low-ks (k~2.5), which are mostly mesoporous (>2 nm) materials that plastically deform from stress. Sidewall pores must be sealed prior to barrier layer deposition.³

"The issues we are worried about for ultralow-k dielectrics already manifest themselves on the low-k materials, such as delamination and even shearing at lower interfaces, which may not be caught right away," said Dave Hemker of Lam's New Product Development Group. He added that many customers will add hard mask or stopping layer late in the development cycle, so tools must have great flexibility. CMP tools also need tighter wafer-to-wafer, lot-to-lot and machine-to-machine control.

Low-k materials keep changing in efforts to make the films harder, with smaller pore size. "There's no doubt that people will select the hardest material they can get. But at some point, you have to make a choice and make it work," said ASM's Werkhoven. Later adopters of low-k films will benefit from advances in hardness. Farhad Moghadam of Applied's Dielectric Systems and Materials Group said, "We did quite a bit of work to reduce pore size and improve mechanical properties, which will help make ALD barriers continuous and IC packaging more reliable."

While Applied is introducing a 10 Å ALD film of tantalum nitride/tantalum for the 65 nm node, other vendors say the next barrier choice is not clear. "TaNSi gets better results and demonstrates some fundamental differences in the way vias behave, so it's not a foregone conclusion to stay with TaN," said Wilbert van den Hoek of Novellus Systems (San Jose).

"ALD's main benefit is managing the line resistance and giving equal or better device reliability performance as with PVD," said Nirmalya Maity of Applied's Copper, PVD and Integrated Systems Business Group. The area occupied by the barrier also decreases significantly. "If you need 10 Å on the via sidewall with PVD, you end up with 50-100 Å on the trench sidewall, whereas with ALD, 10 Å deposits on both sidewalls and is an effective barrier," Maity said. The high cost of tantalum targets and barrier CMP processes indicates overall cost savings with ALD, he added. In addition, IMEC's Maex warned that, while ALD produces almost perfectly conformal films, film continuity must be assured.

With multilayer metal stacks with copper and low-k, KLA-Tencor's Nunan contends that the majority of yield loss for leading-edge devices comes from back-end defectivity. Voltage contrast methods provide the most accurate identification of in-line electrical failures, with a kill ratio very close to 1.0, he said.

Ofer Bokobza of Applied's Process Diagnostics and Control Group said, "We're dealing with the need for increased sensitivity and faster recipe optimization, as well as tighter tool connectivity." Bokobza added that the company is exploring short-loop electrical testing as well as in-line failure analysis.

With wet processes such as electroplating and CMP, the ability to rapidly change process chemistry (slurry chemistry in CMP or H₂O₂ concentration in plating solution) is not nearly as flexible as with CVD or etch processes. Ming Xi of Applied's ECP Division said, "Not many customers have the experience of running plating with reliable filling and defect performance, day to day, over the entire bath lifetime."

"Defect management, the core issue in plating, depends on the additives, the way you introduce the wafer to the bath and how the plating process is started," said van den Hoek. He noted that copper voiding is complex because it can be the result of a discontinuous seed, contamination, or inadequate bottom-up fill.

Copper CMP is challenged to compensate for local and global film nonuniformities, so in situ monitoring of film thickness is becoming more common. "Our real-time profile control is the first step, and now we are working on more advanced control schemes," said Steve Ghanayem of Applied's CMP Division. "There will be more control of the chemistry at the tool level as we go forward," added Lam's Hemker.

Buried defects are a key concern in dual damascene," said Michael Darwin of Rudolph Technologies (Flanders, N.J.). "For process control, you need sensitive high-resolution advanced metrologies that can see below the surface of opaque multilayer film stacks."

Hard masks are increasingly being used in dual-damascene processes. TiN or TaN masks can be very thin, enhancing lithography, and can also act as a CMP polish stop, Lam's Marks said.