Optical System Provides Flip-Chip Timing Measurement
Alexander E. Braun, Senior Editor -- Semiconductor International, 1/1/2003
As geometries have become increasingly smaller to increase device speeds, leakage problems have multiplied. This design concern has re-energized interest in the formation of circuits in thin epitaxial films deposited over an insulating substrate (silicon-on-insulator, or SOI), since being able to eliminate a conductive substrate will in turn minimize leakage and other problems. Thus, many device manufacturers working above five or six metal levels are considering moving to SOI and flip-chip devices, or have already done so.
This trend, however, has created problems in the metrology and inspection areas. With device diagnostic and debug, for example, flip-chip configuration only provides a backside entrance to the active area through the substrate. It prohibits necessary access to metal lines — and therefore to the transistors — to the traditional e-beam probe used to perform measurements required for diagnostics.
Another debug approach, the laser voltage probe (LVP), is also running into difficulties created by smaller geometries and the application of SOI. As a result of design considerations implemented to reduce leakage, both have reduced the very physical phenomena that lent themselves to the application of this technique. Experience appears to indicate that the use of LVP with SOI devices is proving to be difficult and not up to most production levels.
Optonics (Mountain View, Calif.), has come out with its EmiScope platform, which appears to circumvent these difficulties through the use of hot electron/photon emission, a well-known phenomenon that takes place whenever a device switches and draws current. The tool provides a multi-gigahertz bandwidth and an accurate, extendible diagnostic platform to measure switching (timing) events in advanced semiconductor devices through time-resolved, photon-counting emission measurement. It uses optoelectronic waveform acquisition and high-bandwidth timing analysis to detect these increasingly small and extremely fast optoelectronic signals. This results in accurate, transistor-level backside analysis for advanced flip-chip and other semiconductor designs. The system is designed to be extensible to <0.1 µm design rules and <1.0 V operation.
Signal scarcity was the tool's major design challenge, which was solved through high-fidelity collection both in the optics and detector. Everything must take place in the infrared region because the measurement is done through the silicon's backside, and this material only transmits and does not absorb light that is above a 1 µm wavelength. A low-noise detector, with ~10 kHz of noise, was developed with a jitter of ~55-60 psec. The detector's infrared sensitivity is ~50%.
About eight of 10 new packaged silicon devices do not display any physical faults, but still do not function to spec. Device designers look for design failures — resistive, capacitive, perhaps too many delays — to ensure that everything arrives at a NAND gate simultaneously and is not several clock cycles off, out of skew. Generally, the design is based on device simulation packages and other electronic design applications. As the process progresses, the design eventually comes to be represented by the netlist, which is the ID for the different circuits. Through simulation, design engineers identify the top candidates for the different failures. The netlist is connected to the physical design (CAD models) through the EmiScope user interface from the design databases.
The system's imaging is integrated with this CAD layout. When the design engineer selects a particular node or transistor, the microscope travels to it, providing a physical image of the device from the backside, displaying the transistors. The user can now home in on the transistor of interest, and bring it into the 10-15 µm radius field of view, which is the area that gets coupled directly to the detector. (The device being inspected may have a 0.13 or 0.09 µm channel, and can be ~1-2 µm wide.) The tester then is run with the test vectors where the failure or issues of concern have been observed. Here, the light emitted by the transistor is coupled into the fast IR detector. The monitor, like an EKG pulse, displays the signals, enabling the measurement of their frequency and amplitudes. The system is capable of providing high repeatability, and can resolve a transition to within a 10 psec timing accuracy within 3 min.
For additional information on inspection, measurement and test, go to www.semiconductor.net/imt.
