IMEC Investigates High-k Materials for
Sub-90 nm CMOS Technologies

As CMOS devices are built with ever smaller features, the thickness of the conventional silicon dioxide gate dielectric stack must be reduced. When the thickness of this dielectric is reduced to only a few molecules, direct tunneling of electrons through the dielectric significantly increases the leakage current, and device reliability is impaired. Conventional SiO₂ is currently being pushed to its limits.

Researchers at IMEC (Leuven, Belgium) and other institutions throughout the world are seeking reliable materials to replace SiO₂, which has long worked well for larger devices. One way of decreasing the direct tunneling current involves using a material with a higher dielectric constant, or k value, instead of SiO₂ (k=3.9) as the gate dielectric. This allows the use of thicker layers for an identical equivalent oxide thickness (EOT). The greater dielectric thickness should reduce the leakage current, but the preparation of such a dielectric with good uniformity and compositional control, even down to the atomic level, is proving to be a very challenging problem.

IMEC is aiming to achieve EOT values of 0.5-1.2 nm for high-speed, high-performance devices, whereas EOT values of 1.2-1.6 nm are suitable for low standby power logic applications. Gate stacks using a high-k dielectric and either a polycrystalline silicon gate or metal gate electrode must be compatible with standard CMOS processing. They must also provide good electrical performance and excellent long-term device reliability to achieve a 10-year lifetime at the operating voltage.

The IMEC program is now investigating high-k materials including aluminium-, hafnium- and zirconium-based oxides deposited by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD).

For hafnium and zirconium, IMEC is focusing on these pure metal oxides and their silicates and aluminates. Although Al₂O₃ has a suitably high crystallization temperature, a large bandgap and band offset that will reduce leakage currents, its k value is too low to achieve the desired EOT value for devices of the required dimensions. Pure ZrO₂ and HfO₂ were found to have low crystallization temperatures that are not compatible with polysilicon gate thermal budgets.

IMEC has shown that mixing the relatively high-k HfO₂ or ZrO₂ with the stable Al₂O₃ resulted in an enhanced resistance to crystallization, the potential for low EOT values, and low leakage currents (100 mA/cm² to 1 A/cm² is acceptable, depending on the application and EOT target). The mixed oxides may remain amorphous during CMOS processing and provide a sufficiently high permittivity for better scaling of the oxide thickness. "These results are very promising, both for low standby power and for high-performance applications," said Marc Heyns, director of the thin films and ultraclean processing group at IMEC.

Nevertheless, many problems must still be solved to achieve a further reduction in the EOT value to <1 nm for high-performance applications. Surface nitridation of the silicon before the high-k deposition helps prevent uncontrolled surface reoxidation. The researchers found that ALCVD growth of the high-k materials on the hydrogen-passivated surface — obtained after removal of the native oxide by an HF dip — was not planar, and non-uniform growth of islands occurred. However, the interfacial SiO₂ thickness must be reduced because this thickness is effectively added directly to the total EOT value of the dielectric stack. Therefore, a novel pre-treatment step was developed that allows uniform thin ALCVD films to be deposited on native-oxide-free surfaces.

Electron mobility requires further investigation and improvement to meet desired specifications. Strongly degraded minority carrier mobilities were measured relative to the universal mobility curve. The presence of an interfacial oxide improves the mobility and increases the drive current, but at the expense of an increased EOT. Various causes for this mobility degradation were identified, and possible solutions are being investigated. The reliability of these layers is also being studied. When conduction through thin layers of the high-k dielectrics was investigated, a large amount of charge trapping was found in all of the layers, leading to important flatband voltage shifts that threaten the long-term operation of high-k devices.

"No direct solutions are yet available for high-performance applications where very low EOT values are desired," Heyns said. "A few bottlenecks related to the silicon high-k interface properties need to be tackled, and more fundamental research is necessary in various areas. But we are making tremendous progress and are hopeful that we can find a reliable replacement for the successful silicon dioxide gate dielectric in the near future."

For additional information on materials science, go to www.semiconductor.net/materials.