Mixing Signals With 3-D Integration

Wireless products are making mixed-signal IC chips one of the strongest growth sectors of the chip market. From cell phones with an increasing menu of services, to WLAN products and Bluetooth applications, the goal is the same — to provide increased functionality at a lower cost. However, since system-on-a-chip (SoC) was first included in the industry roadmap in 1999, combining analog and digital devices on a single chip rather than in a single package (i.e. system-in-a-package, or SiP) has faced considerable technical and economic challenges. Current 0.13 µm design rules are further adding to the mixed-signal challenge.

A new approach combines the best of both worlds — SoC performance with the flexibility of SiP. Based on an adhesive-less, room-temperature bonding process, this 3-D integration technology brings together, on one chip, devices that are processed on separate wafers yet function as if processed on a common substrate. By implementing standard via and interconnect technology, low parasitics on the order of femtofarads and power consumption reductions of more than an order of magnitude can be achieved, while maintaining between chip speeds of SoC designs.

For generations of devices, analog and digital devices used the same process flow, with analog being the tail wagged by the digital dog. Scaling digital devices to linewidths of <0.25 µm to current 0.13 µm geometries has produced higher volumes of faster devices operating at lower powers. However, analog devices, which are required to interface with the larger "real" world, do not benefit from similar scaling. As design rules approach 0.13 µm, combining analog and digital on a single chip or in a single package faces critical processing and interconnect issues. The problem is that gate oxide thickness and operating voltages are common to all devices on the wafer, analog and digital alike. At 0.13 µm design rules, the scaled-down gate oxide has leakage currents 32× higher than 0.25 µm devices (Table). Similarly, when going from 0.25 to 0.13 µm technologies, core voltages are smaller by a factor of two, decreasing from 2.5 to 1.2 V. These lower voltages save power in digital circuits but constrain headroom and dynamic range in analog circuits.

Ziptronix's proprietary bonding technology enables 3-D ICs to be built using conventional fabrication equipment. A Strasbaugh 7AF precision grinder is shown preparing quartz wafers for rf device integration.

Power requirements vary widely between on-chip and off-chip environments, from 50 to 500×. The disparity in power requirements is clearly indicated in the equation that governs communication between two points, P=C × V²× f, where C is the capacitance of the connection, V the signal and f the clock frequency. The capacitance term is proportional to wire and trace dimensions. For example, the vast majority of on-chip interconnects are on the order of hundreds of microns long, two orders of magnitude shorter than traces on boards connecting one chip to another. Correspondingly, the capacitance term suggests that the power requirement on-chip is orders of magnitude lower than off-chip. Similarly, the voltage term (squared) contributes a factor of seven difference in power, with today's on-chip voltages of ù1.2 V and high-speed interconnect values of 3.3-5. In this case, SoCs provide a better solution, requiring no off-chip communication, while SiP's reliance on communication between discrete devices faces critical power issues.

Ziptronix's bonding technology resolves the power issues of SiP and device performance compromises of SoC. It allows 0.25 µm analog devices with low leakage currents/good operating voltages to be packaged with 0.13 µm, high-speed digital devices, linking them together with standard interconnects.

Key to the bonding process is its repeatability and production-worthiness. Bonding occurs at room temperature, without the application of temperature, pressure or voltage. No chemicals or adhesives are sandwiched between the surfaces, and no inert gases or vacuum are required. Its uniqueness lies in a surface preparation and chemical activation sequence. Called ZiROC, this proprietary process begins with a chemical mechanical polish (CMP) to remove as little as 500 nm of surface material to create the surface finish for bonding. The bonding layer may be any one of a number of common insulating layers, including silicon dioxide, silicon nitride or aluminum oxide.

Each surface is then chemically treated with a sequence of wet and dry processes, which activates the formation of covalent bonds. The enhanced bonding effect induced by the chemical treatment persists for several hours, consistent with the requirements of high-volume, cassette-to-cassette production. Next, the prepared surfaces are brought together, forming a permanent bond.

1. A proprietary bonding method was used to bond two wafers, each with an ~1 µm layer of SiO2. FIB was used to cross-section the wafer and SEM to inspect the bond interface, revealing a seamless bulk-like interface.

In an effort to determine structural integrity under standard semiconductor device processing conditions, the bonded wafers underwent temperature/pressure testing. The bonded wafers were sawed into 2 × 2 mm die, each containing a pressure sensor in the 1.6 mm well. The region under test is a 200 mm bonded rim surrounding the well. Each test die was placed in a pressurized vessel, where temperatures between -40 and 125°C were cycled thousands of times, with 15 min dwell time and 5 min transfer time between temperatures. Following temperature cycling, each die was pressurized at 4 atm. The amount of flexing at the bottom of the well was monitored and used to measure pressure inside the well. If the bond failed, pressure in the well would increase, decreasing the pressure differential between the within-well pressure and vessel pressure. Despite rigorous temperature cycling, all samples showed excellent bonding reliability. The pressure differential remained essentially constant, indicating that the wafer bonding remained intact.

To test interface reliability during standard post-fabrication processing, hermetic testing was conducted in accordance with the fine-leak standard of the MIL-STD-883E testing protocol. Testing was performed on a variety of bonded surfaces, oxide to oxide, silicon to silicon, and SiO₂ to silicon. Wells measuring 5 × 10 mm were etched into the surface of 150 mm wafers. The patterned wafer was then bonded to an unpatterned second wafer. Like the temperature-cycled wafers, these wafers were sawed into die, leaving a 200 µm rim — the test site — around the well. The bonded die were placed in a pressurized vessel filled with helium. Helium measurements were taken upon removal.

2. In all die tested, helium detection was a factor of 10 below the required standard, indicating excellent bond integrity.

Because helium is able to get into the tiniest openings, the amount of helium detected will indicate the smallest leak or porosity that might compromise the seal. In all die tested, helium detection was a factor of 10 below the required standard (Fig. 2), indicating excellent bond integrity. These tests suggest that even a small bonded region of 200 µm is enough to create a strong, effective bond that is able to withstand normal device processing.

The strength of this technique is its applicability in die-to-wafer bonding, making 3-D integration possible. Similar to SiP, multiple chips can be combined in a single package. However, no solder bumps are required. And, like SoC, the structure can be processed with vias, minimizing interconnect lengths. To illustrate the process, consider the addition of memory to a large ASIC. Wafers containing the ASIC and memory devices (e.g. PROMs) are polished with standard CMP to planarize the surface. The PROM wafers are cut into individual die and loaded into a special carrier called a waffle pack. The PROM die and ASIC wafer are then exposed to a sequence of chemical activation steps.

Using a high-throughput, pick-and-place tool with 10 µm registration accuracy, known good PROM die are selected and placed face down on each ASIC die site of the target wafer. When two activated surfaces are brought together, bonding occurs instantaneously. Following population of the target ASIC wafer, the individual PROMs extend out from the surface of the ASIC wafer. A commercial backgrinding technology is used to remove excess substrate from the backside of the PROMs.

3. 3-D integration of a CMOS PROM with CMOS logic, separated by 5-6 µm, was achieved using standard interconnect vias and an adhesiveless, room-temperature, die-to-wafer bonding technique.

Integrating optical chips and electronic components on the same substrate has intrigued the industry for the past 20 years. Because no single material is optimal in terms of electrical and light-emitting properties, attempts have been made to grow epitaxial layers of gallium arsenide (for optical devices) onto silicon substrates (for electronics). Such processes have not yet been successfully commercialized. But even when using such a substrate, co-processing constraints and material incompatibilities will need to be addressed, along with design constraints, which can affect optical efficiency.

High-resolution, state-of-the-art sensor arrays — the heart of today's digital cameras — pack millions of pixels into an area a few millimeters on a side. Because of its diminutive size, on the order of a few microns, each pixel produces a small signal that must travel from interior points out to the edge of the array. To boost signal strength, amplifiers are typically embedded in the array. The electronics needed for amplification, as well as for clocking and I/O, can take up as much as 65% of the area of the chip, leaving 35% for imaging. 3-D integration can change that.

By forming a two-layer structure — bonding a top imaging layer containing the photoconversion pixels to a bottom layer containing the processing electronics — the signal path is reduced by three orders of magnitude, from millimeters to microns. The remaining amplifiers can be hidden behind the imaging layer, thus freeing up space and reducing the number of amplifiers needed. Using this technique, the imaging area could be as high as 90% of the chip area, 2.5× more efficient than standard sensor arrays. The processing of each layer can be optimized for the photoconversion or image processing function to be performed. The two-layer structure also affords closer packing of the pixels, providing greater resolution from a given array area, which in turn can reduce cost while increasing the performance of the optical components.

4. Individual InP optical devices are bonded to within 4.5 µm of CMOS logic devices patterned on a 200 mm wafer. Following removal of the InP substrate, vias are formed between the two die using standard IC processing.

To take full advantage of mixed-signal applications, a room-temperature bonding technique has been developed that effectively eliminates processing issues faced by SoC as well as severe interconnect constraints faced by SiP. An elegant process, it forms a covalent bond between individual die that can withstand conventional interconnect processes. The result is high on-chip performance and low parasitics, high speed and low power consumption, chip to chip.

But the real strength of this die-to-wafer bonding technique is 3-D integration. With the capability of multiple bonding steps, the integration of a memory and an analog device bonded onto a large ASIC is possible. Or additional components could be bonded to a multi-chip module. Work is underway, demonstrating further applications for this production-worthy process.