Strained Silicon Ready for Prime Time

Proof that transistors fabricated with strained silicon were faster due to increased electron mobility and velocity was first demonstrated in the early 1990s, but it wasn't until 1998 that researchers showed it would work with leading-edge, sub-100 nm short-channel transistors. With the ability to increase device performance through continued scaling starting to weaken, chipmakers saw an opportunity in strained silicon to get a fairly dramatic bump in performance with a relatively simple change in starting materials.

Last year, interest in strained silicon soared when IBM announced that it had been able to increase chip performance by 35%, and that it could implement the new technology with minimal impact on existing manufacturing lines (see Semiconductor International , July 2001). Hitachi reported similar results.

Since then, developments have been rapid:

• AmberWave Systems (Salem, N.H.), a new company dedicated to licensing strained silicon technology, was launched in October 2001.
• In August, Intel said it would use some form of strained silicon in its 90 nm node devices (see Semiconductor International , September 2002).
• In September, Unaxis (Truebbach, Switzerland) announced the availability of a new tool designed to deposit strained silicon layers using low-energy, plasma-enhanced chemical vapor deposition (LEPECVD).

At the International Electron Devices Meeting (IEDM), to be held Dec. 8-11 in San Francisco, there will be at least 10 papers exploring various aspects of the technology, including an overview of strained silicon by Massachusetts Institute of Technology's Judy Hoyt (who described the first strained silicon MOSFET in 1992 at IEDM), two papers from Intel and one from Japan's Association of Super-Advanced Electronics Technology (ASET).

The beauty of strained silicon lies in its simplicity. When silicon is grown on top of a layer of silicon germanium, the atoms in the silicon layer align with those in the slightly larger crystalline lattice of the SiGe (germanium atoms are larger than silicon). This increase in spacing between the silicon atoms is enough to change how electrons are shared between the atoms, basically redefining how energy is shared in the conduction bands of the material. "When you split the bands apart as far as energy is concerned, it makes it more difficult for the carriers to scatter, so their transport properties like mobility and velocity are improved," Hoyt said. The result of increased mobility is an increase in channel drive current for a given device design, leading to improved performance.

However, it is not quite so simple as ordering a strained silicon topping from your wafer supplier. For one, the effect on the mobility of electrons — the main carrier in n-channel devices — is different than that of hole mobility, the main carrier in p-channel devices. While it's relatively easy to get close to a factor of 2 increase in electron mobility, it's more complicated to get a similar increase in hole mobility.

The difference lies in the amount of germanium that's required. SiGe layers with germanium concentrations of ~25-30% increase channel drive current up to 35% for n-channel devices, but do little to boost p-channel performance. The hole mobility is only improved if the germanium concentration is increased to 40%. In part, this is because the germanium is not electrically active in n-channel strained silicon devices, but it can be in p-channel. "In NMOSFETs, the silicon germanium is primarily a method of producing that strain or that stress," Hoyt noted. "It gets a little more complicated when you start talking about PMOSFETs. There are opportunities where there would be silicon germanium layers in which the holes might be traveling."

The problem with higher levels of germanium is that it requires more complicated buffer layers to reduce defects. Above a critical limit for thickness and germanium concentration, differences between the lattice constant of the SiGe layer and that of underlying bulk silicon cause misfit dislocations and related crystal defects. These defects cause surface roughness, which lowers MOS transistor mobility and reduces circuit yield.

To control dislocations, AmberWave’s process employs a compositionally graded series of layers of SiGe with varying germanium concentration underneath the SiGe buffer layer. (Source: AmberWave Systems)

Though strained silicon does not require changes in processing tools, there are differences when it comes to diffusion constants, which impact ion implantation and anneal, but that's not necessarily bad. "Some of the dopants diffuse more slowly, which is good because you can control your doping profiles better," Hoyt said. However, "some of the other dopants like As diffuse more rapidly, which is a problem."

For additional information on wafer processing, go to www.semiconductor.net/wafer.