GaAs Wafers Require Special Attention to Overlay

When making use of all the tricks of the trade to achieve finer resolutions with existing lithography equipment, chipmakers must take care to consider what that's doing to their overlay results. Using advanced resists and phase-shift masks to transfer a 0.5 µm gate process to 0.35 µm, for example, may require a tighter registration tolerance.

Paul Duval of Raytheon RF Components (Andover, Mass.) recently studied the effects of various processing methods on overlay measurements for gallium arsenide wafers. His results, which he presented at Interface 2002 in September in San Diego, show that there are indeed significant errors, but that there are steps that can be taken to improve overlay performance.

Raytheon's researchers conducted his studies on Ultratech XLS 7500/2955i steppers, which have overlay specifications of ±90 nm for a single tool to itself and ±130 nm for matching for ultraflat silicon wafers. For GaAs wafers, however, he found it difficult to achieve ±200 nm overlay on gate layers.

But by taking steps such as selecting optimum alignment features, matching each stepper to the master stepper, using dedicated steppers for critical layers, monitoring and controlling chuck and wafer backside flatness, improving reticle alignment and matching, and controlling substrate temperature (more an issue for GaAs than for silicon), overlay performance could be considerably improved.

More specifically, alignment features are usually selected during the stepper's initial qualification, but should be reviewed when process or materials changes are made. Also, all steppers should be matched to a master stepper, but if a stepper's design specifications exceed the overlay tolerances for the new process, lithographers may want to restrict the number of steppers used to print critical layers. In fact, Duval reported that a dedicated stepper approach helped avoid matching problems in his study.

Duval and his team also ran across a problem where the cause of overlay failures could not be easily identified. He eventually traced the problem to stepper chuck contamination, which caused CD variations as well as overlay errors. To counter this, Duval suggests that stepper chuck monitoring be performed at the beginning of each shift.

The researchers found that the largest single contributor to overlay error was generally the mean die magnification variations from lot to lot. Substrate temperature was a significant contributor to this problem, specifically die magnification problems arising from thermal expansion when layer 1 is exposed at one temperature and layer 2 at another. This is particularly a problem for GaAs wafers because their thermal expansion coefficient is greater than silicon. To reduce the errors that this causes, the chill plate temperature must match the stepper environmental chamber temperature, Duval reported.

Although several parameters must be considered throughout the lithography process, Duval concluded that it is possible for GaAs wafers to attain the same overlay results that can be achieved with silicon wafers, despite the need for tighter controls.

For additional information on lithography, go to www.semiconductor.net/lithography.