Transistors With Fins Provide Double-Gate Control

To continue to improve device performance and minimize current leakage when transistors are off, semiconductor manufacturers are beginning to look at some fairly radical new transistor structures that may come into play for the 10 nm generation and below. One of the more promising is the FinFET, first demonstrated by the University of California-Berkeley a few years ago, which features a tall, thin channel and looks somewhat like the dorsal fin of a shark. With this design, not one but two gates are used for control — one on each side of the fin — making it easier to turn off the device. FinFETs are also called double-gated MOSFETs because of this architecture. The approach is radical because CMOS devices are built horizontally, while FinFETs are built vertically. Unlike other double-gate structures, however, the FinFET can be fabricated with minimal deviation from standard CMOS processes.

At next month's International Electron Devices Meeting (IEDM), to be held Dec. 8-11 in San Francisco, a variety of papers will be presented on FinFETs. Some of the most noteworthy examples, culled from pre-print abstracts provided by conference organizers, are outlined below.

An IBM paper will describe a technology that combines metal gates and FinFETs with a correction for threshold voltage. It represents both the first time that metal gates have been successfully integrated in a double-gate architecture, and that a double-gate device matches or beats the on/off performance of traditional CMOS technology. The devices were fabricated with undoped body, raised source/drain, CoSi₂ on the source and drain and an NiSi gate (Figure).

A TEM view of a cross section of a metal-gate FinFET, taken perpendicular to the direction of the fin. (Source: IBM)

To fabricate the FinFET devices for the SRAM, IBM started with an SOI wafer with a 160 nm active silicon layer, which was oxidized to form an 80 nm SiO₂ layer, thereby thinning the silicon to 120 nm. This was followed by the deposition of a nitride layer. Deep ultraviolet lithography was used in conjunction with a specially designed silicon-island mask. After some etch-back of the hard-mask layers, the silicon fins were etched, achieving a fin thickness of 60 nm. A 2.2 nm gate oxide was grown after a sacrificial oxidation of the fin sidewalls and a 75 nm poly gate deposited, patterned and etched. Remaining hard mask on the tops of fins and contact regions was stripped using dilute HF and followed by a 3.5 nm oxidation of the polysilicon gate sidewalls. Threshold voltages were centered by angled implantation of boron and phosphorus halos for nFETs and pFETs, respectively, concurrently with extension implants. Nitride spacers were formed on the gates and fins. CoSi₂ was formed on gates, sources and drains, with the sides of the fins protected by the spacers. A nitride passivation layer was followed by PSG and planarization. Subsequent interconnect levels were conventional copper damascene.

Researchers from Advanced Micro Devices (Sunnyvale, Calif.) will show that FinFETs may be a better choice than conventional transistors for extremely small devices. They will demonstrate how they built fin widths and gate lengths down to below 10 nm using a modified CMOS process. They used a 17 Å nitrided oxide gate dielectric and achieved excellent control of short-channel effects and leakage current. They say that, while much needs to be done to perfect the technology, it is an excellent candidate to replace standard CMOS below 20 nm.

Researchers from Taiwan Semiconductor Manufacturing Co. (Hsinchu, Taiwan), meanwhile, made a gate shaped like the Greek letter omega — called the Omega FET — that surrounds almost an entire 25 nm silicon channel. They built the device in two versions: a 1 V version that demonstrated low current leakage, and a 0.7 V version with gate delays, said to be the lowest among all reported types of 25 nm devices (39 psec/nFET, and 88 psec/pFET).

For additional information on emerging technologies, go to www.semiconductor.net/emerging.