IMEC Explores Interconnect, Reliability Issues Beyond 65 nm

With activities ranging from device design and CMOS integration, to MEMS development and reliability, IMEC (Leuven, Belgium) is well positioned to take a holistic approach to microelectronics research. While most companies are being forced to drastically cut resources, this research house is expanding its programs and building a 300 mm development line.

IMEC's work in the area of interconnect technology alone takes a three-tiered approach: current integration of low-k dielectrics in copper dual-damascene schemes; use of wafer-level packaging layers that integrate high-frequency passives and other functions; and a system-level approach based on device application. "Wafer-level packaging is being optimized to allow the interconnect's use as a transmission medium rather than just electrical interconnection," explained Eric Beyne, director of enabling technologies for distributed and autonomous electronic systems at IMEC. While the need for comprehensive approaches is most evident in system-on-a-chip and system-in-a-package designs, it also extends to mainstream silicon devices. IMEC is attempting to characterize all possible wiring solutions on and off chip, including optical interconnects.

CMOS scaling inevitably increases the electrical fields and current densities on the chip, leading to a decreasing reliability budget for each circuit element with each new technology generation. "Reliability is becoming a major bottleneck in the further downscaling of VLSI technologies," said Guido Groeseneken, group leader of technology reliability and yield at IMEC. "New materials and processes are being introduced faster than the capabilities to understand their reliability properties and failure mechanisms." IMEC advocates reliability assessment of new materials "as early in the design phases as possible," to expedite the creation of functional and reliable devices.

A sputtered TaN/Ta barrier film effectively sealed a mesoporous low-k film. (Source: IMEC)

With advanced low-k dielectrics, several questions arise. If pores are added, how much porosity is tolerable in an interlevel dielectric? Are the pores small (nanoporous, <2 nm) or large (mesoporous, >2 nm), and can these pores be sealed off? At what point do porous sidewalls lead to porous metal barriers?

IMEC is evaluating seven low-k materials, including LKD 5109 (k~2.2) and LKD new (k~1.9) from JSR, Zirkon (k~2.2) from Shipley, porous SiLK (k~2.2) from Dow Chemical, BD II (k~2.4-2.6) from Applied Materials, Aurora 2.4 (k~2.4-2.6) from ASM and an unidentified CVD film (k~2.2), possibly from Dielectric Systems. Maex explained that the difference in behavior between nanoporous and mesoporous low-k films is actually more significant than whether the film was deposited by spin-on vs. CVD. IMEC is simultaneously testing low-k hard masks from Dow Chemical, Shipley, JSR and Dow Corning (SiC, k~4.2-5.0). She emphasized that, since k_eff is the key to performance, the k values of hard masks and etch stop layers can be more critical than the k_ILD.

Four key issues will determine the limits of k value in production, Maex said. These include the ability to both seal the pores and analyze sealing defects, to determine the electrical impact of sealing defects and characterize/ensure barrier integrity. "These are enabling steps for production and will ultimately define the lowest k value for production," she said. Currently, there are three methods for sealing pores: by bombarding low-k sidewalls using a plasma; by oxidizing the sidewall to create Si-O-Si bonds; or by chemically polymerizing the film, producing cross-linked C-C bonds. Plasma treatment has the effect of shrinking CD, whereas oxidation usually elevates k value. The chemical approach is interesting due to its potentially minimal effect on both. In metrology, chemical absorption can identify sealing defects as small as 6 Å.

In metalization, advanced PVD layers have demonstrated compatibility with sealed mesoporous low-k films (Figure). However, Maex notes that sidewall sealing is not effective for all low-k materials, and may play a significant role in material choice. IMEC is also developing ALD barrier/seed layers with the goal of obtaining similar performance to ionized PVD approaches (via resistance and chain yields), with ultrathin films (5 nm) that integrate with various low-ks.