Designing for High Product Yield

The strength and competitive advantage of a fabless semiconductor company reside in its designs. Nevertheless, high yield, especially in the early stages of a product's lifecycle, is equally important for the success of the company. Traditionally, the primary strategy adopted to increase yield is to shrink the layout, leading to ever smaller standard and SRAM cell sizes and denser routing. However, the simple chip-shrinking approach is complicated by the relationship between the myriad detailed design rules derived from the complex interaction between the product layout and the wafer manufacturing process. Once largely a function of critical area, yield loss is increasingly a function of critical features such as contacts and vias. Even for defects caused by random particles, layout details determine the extent of yield loss.

Due to these complexities, yield depends more on design attributes than on total chip area. By understanding this functional dependence, device designers can design for maximum yield and make accurate yield predictions. We describe a yield impact matrix methodology that combines design attributes and technology characterization data to predict the yield. The methodology has been applied to advanced yield ramps at major semiconductor manufacturers. The circuit designer can use this methodology to ensure high-yielding chips.

Rapid yield learning is critical for the profitable production of ICs in today's semiconductor business, where multibillion dollar semiconductor fab facilities confront increased time-to-market and time-to-volume pressures. To be profitable, the cost per good die must be minimized by quickly ramping yield to an economically acceptable level. Predictive yield modeling can be used for accurate yield prediction in all stages of product design and production, thereby maximizing chances of high insertion yield.

Traditionally, yield is calculated based on the defect density (D₀) of a foundry process and die area. Unfortunately, if the goal is to design for maximum yield, the only "knob" that can be twisted is to shrink the design. This increases standard cell densities, reduces SRAM cell size, and generally shrinks anything that impacts the total circuit area. However, any of today's design rule manuals for deep-submicron technology typically include complicated rules for contact borders, polysilicon end-caps, metal line ends, density, etc. These rules have been derived from the interaction of the design layout and wafer process requirements such as alignment tolerances and many other constraints. Even for the random defects caused by particles, the details of the product layout determine the critical areas (die locations where the presence of a given size particle will impact yield). Because of these interactions, device yield is driven more by design attributes than by the physical chip area.

Important yield loss mechanisms in state-of-the-art ICs fall into several categories. Process-related yield losses dominate and are caused by factors such as misprocessing (e.g. equipment problems), systematic effects (e.g. alignment or printability problems), and random defects (e.g. particles/contamination). High-performance ICs may exhibit design marginalities; they are not sufficiently robust to withstand either process fluctuations (low C_pk) or environmental variations (e.g. supply voltage or temperature).

During previous technology generations, random defects were the dominant yield loss mechanism. This condition has changed significantly for 0.18 µm and smaller technologies, where random defects typically contribute <45% of the yield loss. Incompatibilities between design and process, primarily systematic in nature, are most critical due to increased device and process complexities and often subtle interactions.

PDF Solutions adopted a comprehensive methodology for modeling yield loss mechanisms. It combines extensive technology characterization with design details to generate a yield impact matrix (YIMP) that can pinpoint problem areas in a product layout. We present the methodology using real-life examples.

In general, three steps are necessary in predictive yield modeling: 1) detection and classification of defects; 2) estimation of how many of such defects can cause product failures; and 3) calculation of the expected yield loss for each defect type.

The process of quantifying yield loss involves three steps. First, defects are detected and classified — a difficult task in itself. One option is to design and manufacture technology-specific characterization vehicles (fast turnaround test chips) and compile the test results from the completed chips.¹ Discussion of characterization vehicles is beyond the scope of this article. The second step involves predicting defect occurrence frequency using various mathematical models and algorithms, as outlined in the next section. All such methods are designed to estimate the failure rate, l _chip, which is the expected average number of chips killed by each defect type. The third step is to use the l _chip for each defect type to calculate the limited yield for each defect classification.

We calculate yield impact predictions by combining process defect rates with design attributes (e.g. critical area, via and contact counts) based on the chip layout. We define two important parameters used in this flow analysis: defect size distribution (DSD) and critical area (CA), both as a function of defect size, x. The DSD describes the probability of occurrence or count of defects as a function of defect size.

Using the following equation, we can extract parameters, for example, from characterization vehicle test data. The function, f(x), is a scaling function, and k/x^p is the size distribution function that integrates to a value of 1.0 between x₀ and infinity.

The second parameter of interest is CA(x), which describes the area of the chip that would fail if a defect of size x is present. The failure rate, l _l, for a single planar interconnect layer, l, is then:

We then use this failure rate to predict the limiting yield, Y_n, for a specific layer, n, using the Poisson distribution:

For via layers, the limiting yield for individual blocks such as Y_{l via} is calculated using the number of vias in the chip and the failure rates for single vias extracted from characterization vehicles.

1. The defect size distribution describes the probability of occurrence or count of defects as a function of defect size (x) and chip area (Ac).

Figure 1 graphically shows the results of this analysis, while Table 1 gives the yield impact matrix.

If the process layer in this table are chosen in such a way that various design attributes are counted only once, overall chip yield is simply the product of the entries in one column. In the above example, we expect a chip yield of 46%. The active area contact yield and polysilicon contact yield primarily determine chip yield. Yield can be improved by adding redundant contacts. If we can add redundant contacts in 50% of the instances, overall yield improves to 55%.

We can expand this basic concept by breaking the chip into multiple independently tested blocks of synthesized logic, embedded memory, and proprietary circuitry or intellectual property (IP) blocks. The preceding analysis can be applied to each component of the chip and yield matrix (Table 2). In this case, yield is most limited by logic and embedded IP blocks. Embedded SRAM is less of an issue. Within IP blocks, vias between metal-2 and metal-3 pose the largest concern. Although memory yield is not a large factor, it is evident that the memory core, rather than the peripheral circuitry, determines the memory yield. Thus, modifications to the SRAM bit cell provide yield improvement opportunities, allowing designers to focus efforts on areas that will provide the greatest improvement.

YIMP applications

The example above can be used to analyze product design before tape-out to estimate pre-silicon yield and make necessary adjustments to the design before committing to silicon. However, the YIMP methodology also can be used for:

• Calculating the appropriate amount of memory redundancy.
• Determining the estimated die yield for capacity planning.
• Predicting product costs for budgetary and ASP determination.
• Benchmarking internal design methodologies based on yield.
• Determining systematic yield-limiting design attributes.
• Comparing IP blocks based on expected yield.

The following examples compare different chip designs, foundry capabilities and actual vs. modeled yields.

Let us assume that Company A is defining a product that is targeted for Foundry X. The product includes an embedded SRAM chip, the size of which may be increased by 50% so as to offer several additional features not offered by a competing product. There is a need to quantify the yield and die cost to choose the best chip architecture.

The calculation in Table 3 indicates that the larger memory chip (BB) will increase die cost by 18% relative to the initial design (BA). However, if we add a small amount of memory repair (BC), we can dramatically improve SRAM memory yield, thereby reducing the die cost from $26.32 to $19.05, below the initial design cost, while adding important features.

The next analysis can be used to benchmark foundry performance. Company B has been using Foundry X to manufacture the majority of its product AA. Foundry Y provides the same wafer fabrication process at a lower price per wafer to attract new customers. Moreover, Foundry Y will provide guaranteed wafer capacity. Does it make sense to switch?

The YIMP analysis (Table 4 ) indicates that, despite Foundry Y's lower wafer price and higher yield for active area contacts, overall yield is lower and cost per good die is higher. Company B needs to either negotiate a lower price with Foundry Y or make design changes to improve the overall yield for this fab process.

Finally, by comparing actual wafer fabrication and testing yield with YIMP-based yield predictions, one can reveal yield gaps, such as those shown in Figure 2. In this example, scan chain #5 shows a substantial yield gap, suggesting that our model is missing some systematic component in that chain. Events such as antenna-related plasma damage or a peculiarity in the layout design of specific blocks may explain this behavior.

2. The yield gap between actual and predicted yield reveals areas where the causes of yield loss have not been sufficiently characterized, for instance, in scan chain #5.

By implementing a comprehensive predictive yield modeling approach, companies can better meet the challenges of time-to-volume and time-to-money. This versatile methodology can be used to predict yields, implement design for manufacturability solutions and speed product failure diagnosis. This approach has been field proven in numerous applications.