Is Your Package Causing EMC Failures?

An important criterion for the sale of any electronic product in the United States is certification that it passes the electromagnetic compliance (EMC) requirement of the Federal Communications Commission (FCC), in either Class A (commercial environment) or Class B (residential environment).

Virtually every large OEM has a horror story of product ship delays or even cancellations due to a fully functional product's inability to pass FCC certification, which couldn't be fixed in time to catch the market window. The place to look to fix EMC problems may sometimes be the package and chip layout.

The efficiency of a product to radiate typically scales with the bandwidth of the digital signal. As clock frequencies increase, the bandwidth of signals increases and the radiated emissions will inevitably increase. Only ~10 nW of power radiated in the bandwidth of the test will cause a chip to fail an FCC Class B test. This is an incredibly small amount of power. As clock frequencies increase, EMC problems will only get harder to solve.

Near-field scan of a 132-pin quad flat pack showing electric field hot spots. (Source: Kevin Slattery)

What makes the source of EMC problems particularly difficult to pinpoint is that even a product that meets the performance spec, and has no signal integrity problems, can still fail an FCC test.

Kevin Slattery, a staff engineer with Intel (Hillsboro, Ore.), relates an experience he had years ago at Daimler-Chrysler Electronics (Huntsville, Ala.). Six identical timer chips were obtained from six different vendors and mounted on six identical boards. Each board had identical performance, yet one of the boards had >15 dB higher radiated emissions than the others.

Slattery ultimately traced the problem to the layout of the power and ground distribution on the chip itself. "Most solutions for EMI (electromagnetic interference) address the board design real well but not the chip or package design," he said.

At the IEEE EMC Conference held in Minneapolis in August, Slattery presented examples of four valuable tools to evaluate the EMC behavior of packages: shielded room far-field measurements, GTEM (gigahertz transverse electric and magnetic field) cell table-top measurements, 3-D full-wave simulations, and near-field scans. He showed that, with the excellent agreement between shielded room, GTEM cell measurements and simulation, it is practical to use GTEM and simulation tools to substitute for shielded room measurements in the design phase.

While a near-field scan will not correlate perfectly with far-field emissions, it quickly identifies electric or magnetic field "hot spots" often related to higher ground bounce noise voltage. Though sometimes not enough to cause performance failures, excess ground bounce will drive radiated emissions either directly from the package or indirectly in cables. "Reducing hot spots in chips and packages will reduce the cause of radiated emissions," Slattery said.

Hot spots can be reduced by spreading out the power and ground distribution on chip, adding on-chip decoupling capacitance, adding more power and ground pins to the package and spreading out the current distribution over all the pins, using more power and ground layers in the package, and using on-package decoupling capacitors.

Using GTEM cells, full-wave simulation tools and near-field scans as probes of EMC performance in the package design phase, the final EMC performance of some packages has been dramatically improved. For example, multiple power and ground planes are commonly found in high-performance, high-pin-count packages. These tools helped Slattery and his team determine that, by using the outermost layers as ground, recessing the power planes in from the edge, and stitching the ground planes together with vias along the edge, the board-level radiated emissions decreased by 15 dB in some cases.

Traditionally, EMC engineers pay attention to the power supply, enclosure, external cables and board design. As clock frequencies deeply penetrate gigahertz rates, the package will be a significant contributor of EMC problems and should be evaluated early in the design cycle.

For additional information on semiconductor packaging, go to www.semiconductor.net/assembly