Dielectric Etch Looks for Processing, Metrology Solutions

Etch complexity has grown alongside that of the products it processes, now requiring complex, million-dollar chambers with multiple-frequency generators and advanced process control (APC). Increasingly sensitive photoresists, depth-of-focus factors, and exotic chemistries have led etch to a technology crossroads (Fig. 1).

"The dielectric market is separating into two areas," said Jeff Marks, vice president for the Dielectric Etch Group at Lam Research Corp. (Fremont, Calif.). "At the copper back end with low-k materials, there's a unique set of requirements, especially relative to the various materials used in dual-damascene structures. In front-end applications, aspect ratios and feature sizes will be challenging. Add 193 nm photoresist's quirks, and etching these high aspect ratios and small CDs with thin resist becomes complicated."

"Etch isn't a low-k showstopper. For high-k, it requires learning to etch relatively non-volatile materials," said Jim McKibben, vice president, worldwide marketing and sales at Tegal (Petaluma, Calif.). "These transition metals' oxides, silicates and titanates are difficult to etch, requiring novel electrode materials. Result? You must learn how to etch metals like platinum, perhaps iridium, or tantalum."

Copper dual-damascene etching started with a trench-first, via-last scheme, said Amulya Athayde, director of product marketing, Dielectric Etch Division, at Applied Materials (Santa Clara, Calif.). "As the industry moved to 0.13 µm it has reversed — via-first, trench-last. This has been driven by lithography alignment issues and the need to eliminate a middle-stop layer. There'll be more changes at 65 nm, with porous materials being introduced and the adoption of hard-mask schemes."

1. There are no one-size-fits-all solutions for dielectric etch’s demanding requirements. Technology will have to be quickly developed to cope with the plethora of new materials, processes, and metrology and APC requirements. (Source: Lam)

The principal challenge is maintaining critical dimensions (CDs) of etched features. Trench etch, particularly when done after defining the via, can be influenced by different phenomena including fencing, microtrenching, and linewidth and depth variability, all affecting the copper interconnect's electrical characteristics. These are concerns for FSG, especially for low-k materials. "With CDO low-k materials, other hurdles are maintaining k-value stability and eliminating fluorine memory effects," Athayde said.

Selectivity is important at the bottom stop layer (BSL), where the copper layer is in the trench-first, via-last scheme. "With via-first, trench-last, the BSL is twice exposed to etch," he explained. "Selectivity's crucial during via etch, and trench etch requires a protective material at the bottom. Fabs want the BSL very thin, but if breached it compromises the subsequent metal interconnect's integrity. Although it's possible to adjust for uniformity, doing it wafer-to-wafer is complex — selective processes are necessary."

Fluorine memory effects are strip-related. Polymers deposited on the wafer during etch protect sidewalls and maintain the profile, help with selectivity and protect the photoresist. However, polymers also deposit on chamber surfaces and residues build up. When the wafer is stripped in the same chamber, fluorine from the decomposed polymer is released and can attack features on the wafer. Trench etch is most affected by fluorine memory effects. Fluorine can enlarge the CDs of damascene trenches after stripping, with potential impact to interline capacitance. This is more serious for low-k materials such as carbon-doped oxides (CDOs), which are more sensitive to isotropic etching than oxides.

"A typical damascene trench etch process sequence starts with the trench etch, going to resist stripping and stop-layer removal, with potential intermediate wet process steps, before the wafer goes to metalization," Athayde said. "The conventional approach has been to run the process sequence with each step in a different tool." If the steps are done separately, fluorine problems are avoided, but the multi-step has high costs associated with throughput.

According to Applied, combining all etch steps on a single tool, eliminating any intermediate wet process steps, can reduce cycle time and work-in-process inventory. "Running all etch steps — trench etch, resist strip and stop layer removal in a single chamber — introduces a process interaction potential, leading to fluorine memory," Athayde said. "By isolating processes to individual chambers on a single mainframe, you get the benefits of a simple process flow, but without process interaction or fluorine memory issues." Applied proposes segregated chambers in a multi-chamber tool, so that one does the high-selectivity chemistry (via, trench) etch, and another the "clean mode" — strip and stop-layer removal. Eliminating process interaction reduces development time for low-k dual-damascene etch, and allows individual process steps to be tuned for optimal results, avoiding problems such as wafer arcing (see "Wafer Arcing — Etch's Secret Hurdle").

Michael Mills, applications director, semiconductor fab materials at Dow Chemical (Midland, Mich.), doesn't view low-k as exotic. "It's just a materials set that we're unacquainted with, as we've migrated from oxides and FSG. I lump them together because they're solid, hard, put down the same way, and copper's integration scheme is identical — full via first, and no CMP stops on top." However, low-k is different. In particular, a significant amount of organics are incorporated into a silica-based network — whether CVD-OSGs (Black Diamond, Coral or Aurora) — or applied chemically, achieving the same result by a spin process, SOD-OSGs.

The second set is the wholly spin-on organic interlevel dielectrics (ILDs), where the material is 100% organic instead of a hybrid like organosilicate glasses (OSGs). "SiLK and GX3 are organic — important for etch benefits like selectivity and no resist poisoning issues," Mills said. "Low-k integration is converging on a single process, different from the one for USG and FSG where everything is etched, leaving the copper cap for subsequent etch process. The same ashing tools are used because they're all inorganic materials." For low-k materials the dielectric — OSG or SiLK — doesn't react well to standard non-selective techniques like ashing. Ashers don't distinguish between photoresist and the organic component of an OSG or SiLK film.

An IBM process using two thin hard masks on top of the low-k material — when they chose SiLK for 130 nm — demonstrated the possibility of etching the photoresist pattern into the top hard mask, whether the via pattern or the trench. Here was an organic resist on top of an inorganic. The top layer is typically silicon dioxide etched to ~1000 Å. Then the ashing tool strips off the photoresist, while the underlying hard mask protects what's underneath. The next step is to put a photoresist for a via if trench first is required, open the second hard mask, and etch through the low-k material. Unique to ILD organics like SiLK, the resist is consumed during this multi-step etch process, eliminating 50% of the ashing steps required for dual-damascene integration.

"OSG requires an etch chemistry that removes organic and inorganic at the same rate," Mills said. "The obstacle is that the top hard masks — inorganic materials — hold CD, and the etch chemistry takes out every material set. Selectivity's an OSG issue: profile and CD; another is sidewall damage. If organic and inorganic aren't etched at the same rate, somewhere further into that material the second phase has been removed faster than the first — an etch selectivity issue." When etching organics, the process goes through the pattern, the trench on the top hard mask and the via begins being etched. Afterward, the first layer of SiLK is etched. Chemically, to the plasma, SiLK looks like photoresist so it's consumed during the SiLK etch. The hard mask, with SiLK selectivity, provides CD control, eliminating a second ashing step.

With dual damascene, there are different films in the back end — low-k — structures needing etch, said Lam's Marks. "You must etch one material, be selective to another, and then reverse it. In an ideal reactor you want the capability to etch the front end, the dual-damascene back end, and for large exposed areas."

Dual-damascene structures demonstrate integration scheme complexity, said Jim Tietz, managing director of Lam's Dielectric Etch Product Group. "The materials' variety and film sequencing, to which etchers must react, makes seemingly mutually exclusive demands on the platform. For front-end applications, in situ processing is used. You dig a deep hole with polymerizing chemistries, then to do a strip and barrier open you require a different process. The reactor must address multiple needs in one wafer pass. With so many films and integration sequences, standardized processes no longer exist."

Marks agrees. "We must go from etching with high selectivity to 193 resist, to uniform stripping capability. With dual-damascene applications, there's typically a resist etch back process to recess the plug — how do you do this uniformly in a reactor designed to be selective to photoresist? Designing a reactor to change behavior is like building an automobile that can be used off-road like an SUV, changes into a two-seat convertible when you're on a date, and into a minivan to go to the store." In today's process flows, even within a given etch step, there's a variety of hard-mask materials — the barrier, porous low-k material — with different etch requirements. Lam is banking on dual-frequency capability, with a confined plasma as a solution.

"Flexibility and cross-contamination don't mix," Marks continued. "You're often working with incompatible chemistries. We've addressed that by designing the reactor to run in a clean mode. The requirement is to run different etches, such as in a low-k, dual-damascene integration flow, where you have organic and inorganic materials. Users want both because some use SiLK, others SiOC films. This indecision requires additional development work, delaying low-k adoption — you need an assortment of baseline processes. Smarter tools and better process control are needed."

2. Dual-damascene etch of an all-spin-on low-k film. (Source: TEL, Dow Chemical)

Dave Hodul, applications manager at Therma-Wave (Fremont, Calif.), regards dielectrics from a metrology perspective. "In terms of future etch metrology needs, film stack measurements aren't too different from those for today's stacks. Metrology for etch materials in low-k and those for etch on SiO₂, TEOS, FSG, and so forth is similar."

The difficulty in measuring film stacks — CVD, organic and spin-on materials — is the thin etch stop layers between these materials' thinner layers; optical and other properties differ. "The properties give us needed contrast. For metrology purposes, their refractive index isn't complex — the seven- or eight-layer stacks used with etch stops probably aren't challenging in the case of standard low-k — Black Diamond, Coral or SiLK. However, organic films have thin adhesion layers in between — tenths of angstroms. Measuring these is complicated," Hodul said.

Aspect ratio is another concern. Light must propagate into the trench and be reflected or refracted out. "Some claim that the biggest barrier to ultralow-k isn't integration, but as-yet-undeveloped metrology," Hodul explained. "Before, only thickness measurements were required. Now it's materials properties, pore sizes, pore shape, pore distribution and so forth. Most pore size and pore distribution measurement technologies are expensive — low-angle X-ray scattering, vacuum techniques, etc. To determine pore size you need a probe with a wavelength on the order of those pores." Visible light may be inadequate, and using electrons or protons with the proper length scale is expensive, slow and destructive.

3. Atomic force microscopes and atomic force profilers can measure depth in actual high-aspect-ratio features, rather than the large open areas traditionally used to monitor etch depth. (Source: Veeco Instruments)

People are more discriminating about measurement, said Rich Quattrini, director of marketing, CD metrology products at KLA-Tencor (San Jose). "Before, they measured simple widths of trenches and holes. Now they must know more about the integrity of the pattern transfer process. For trenches, the depth and overall shape are equally as important as the width. For holes, diameter measurement isn't enough.

"Metrics that are more closely related to the electrical properties, such as the hole's total area and its integrity at the point where it touches the underlying layer, are more important. Integrity can mean wall edge roughness, wall profile — even overall hole shape, because these can be round, elliptical, or nearly square depending on the optical extension technology applied."

No technique measures everything that the customer wants. "Can CD-SEMs provide precise and accurate enough depth measurement for trench?" Quattrini asked. "Is a scribe line optical test grating enough to indicate what's going on inside the chip, given that you have microloading and other spatially related effects? Are AFM and dual-beam FIB techniques really up to the demands of volume production?"

A CD-SEM provides top-down 2-D information, unobtainable through optical or other techniques. The CD-SEM can give shape, and area, and edge wall roughness. Inside the chip, where the source/drain contacts and gate contacts have different depths, it can selectively measure contacts and provide unique process control statistics. However, with new low-k materials, sample charging makes measurement difficult. "Some low-ks show up black because sufficient electrons cannot be collected for imaging," Quattrini said. "We've developed techniques for charge control and management to get enough signal to see the bottom."

CD-SEMs are being equipped with beam-tilting capabilities for triangulated trench depth measurement. They also provide 3-D profile reconstruction to a first order, provided features have reasonably defined edges with minimum curvature. "With current optical measurement techniques, we can determine depth to a couple of tenths of a nanometer," Quattrini explained. "The biggest issue is confidence in the correlation to actual device structures. You measure a grating that simulates device structures with similar linewidth and pitch. Many fabs are finding this is enough to give them satisfactory correlation to what's happening inside the device. Some fabs, however, still have concerns. This is particularly the case when complicated lithography assist structures are used differently in critical areas inside the device than they are in long and straight diffraction gratings. At day's end, someone must make a call on what's the most effective process control technique for a particular device and layer. There's no perfect metrology technique — we're all still searching for the Holy Grail."

With dielectric etch, each choice — whether materials or metrology — is a trade-off. There are no one-size-fits-all solutions. Until now, the industry took for granted how easy it was to rework lithography in the back end. This is no longer trivial with low-k. If leading-edge resists show sensitivity to plasma etch, there will be problems with edge selectivity resist to the underlayer that could become CD control issues. Resists are getting less robust, APC increasingly expensive, and no one foresees magic cures.