Intel Unveils 90 nm Process

In August, Intel Corp. (Santa Clara, Calif.) officially took the wraps off its new 90 nm process, which it says it will put into volume manufacturing next year using 300 mm wafers. The new process combines higher-performance, lower-power transistors, strained silicon, copper interconnects and a carbon-doped low-k dielectric material. Intel says this is the first time all of these technologies will be integrated into a single manufacturing process.

"While some are slowly transitioning production to 130 nm (0.13 µm) process on 200 mm wafers, we are moving ahead with the most advanced 90 nm technology exclusively on 300 mm wafers," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group. The new 90 nm process will feature transistors with a 50 nm gate length (Figure). By comparison, the transistors in Intel's Pentium 4 processors measure 60 nm. The transistors feature gate oxides that are only five atomic layers thick (1.2 nm).

Intel has integrated its own implementation of high-performance strained silicon into this process. The benefits of strained silicon are that electron and hole mobility is increased in transistor channels, resulting in a 10-20% increase in transistor drive current, said Mark Bohr, Intel fellow and director of process architecture and integration. The process doesn't degrade transistor short-channel behavior or junction leakage, and adds only ;2% to total processing costs.

The transistors implemented in Intel’s new chipmaking process are the smallest ever to be designed into a commercial microprocessor, measuring 50 nm. (Source: Intel)

Strained silicon transistors are only one of several non-classical CMOS designs that researchers are studying, including ultrathin-body silicon-on-insulator, vertical transistors, double-gate transistors and FinFET transistors (see Semiconductor International , March 2002).

Earlier this year, Intel used its 90 nm process to make the world's highest-capacity SRAM chips at 52 Mb (capable of storing 52 million individual bits of information). These fully functional chips pack 330 million transistors in an area measuring only 109 mm² (see Semiconductor International , May 2002).

"Intel's 90 nm process is very healthy today, and we are routinely producing these wafers and chips in our development fab," Bohr said. "By next year, we will be the first company to have a 90 nm process in volume manufacturing."

Intel's 90 nm process also integrates seven layers of high-speed copper interconnects, which increase processor performance. A combination of 248 and 193 nm lithography equipment is used for this process. The company also expects to reuse about 75% of the process tools used on the current 300 mm version of its 0.13 µm process, lowering implementation costs and ensuring a mature toolset for the manufacturing ramp. The 90 nm process will be ramped into high volume in D1C and transferred to other 300 mm manufacturing fabs starting next year.

In a related story, despite a significant increase in Intel's average die size, considerable investment in new fabs and a ramp-up in 300 mm wafer production promises to keep Intel ahead of its competitors, according to Reed Business Information's In-Stat/MDR. The high-tech market research firm estimates that Intel's quarterly wafer-area production will double by the end of 2003 (vs. 1Q01), and by the end of 2004 the company should be producing more than 700,000 (200 mm-equivalent) wafers per quarter.

Recently, the significant cost advantage that Intel has held over its competitors in the past has diminished, and has actually been reversed in some cases. With the introduction of the Pentium 4 processor, Intel's average die size (and associated costs) increased significantly in 2001— a trend that continues into 2002. Larger cores and die sizes will continue to push Intel's average die size higher, until the 0.13 µm process ramps up in volume in 2002 and reverses the trend. Average die size should stabilize and begin to trend down with the introduction of the 90 nm process in the second half of 2003. The lower cost of 0.13 µm 300 mm wafers will help lower the cost of all Intel products, especially server processors, whose die costs are much higher than their packaging and test costs.

For additional information on wafer processing, go to www.semiconductor.net/wafer.