New Bonding Process Offers 'Penalty-Free' 3-D Integration

"We're going to do for the semiconductor industry what steel did for the building industry," says Doug Milner, CEO of a new company called Ziptronix (Research Triangle Park, N.C.), a spin-out of the Research Triangle Institute (RTI). This is no idle boast: He's talking about a bonding process that was under development at RTI for the past eight years and that Ziptronix — the first spin-out of RTI — is now in charge of commercializing.

The "zip" in Ziptronix stands for zero integration penalty, and that's what Milner claims is possible with the company's material bonding process, which works at room temperature, employs standard fab process equipment and results in a very strong covalent bond. He expects it to enable the fabrication of 3-D devices without the compromises or costs associated with system-on-a-chip (SoC) or system-in-a-package (Figure). The company also sees benefits in fabricating MEMS and rf devices, as well as more exotic applications like indium phosphide on CMOS. "We have proof of concept projects in each one of those areas that are active now," Milner said. "We anticipate that we'll be in production in the engineered substrate space by the end of this year."

3-D integration of a CMOS PROM with merchant CMOS logic. The two devices are separated by 5-6 µm, allowing easy interconnect via peripheral pad rings or by standard vias cut through the Ziptronix bond interface. The benefit is the performance of an embedded memory without the cost penalty of increased die size. (Source: Ziptronix)

The bonding process is performed at room temperature without adhesives, and utilizes standard manufacturing equipment and chemicals. The mechanical wafer preparation is based on a standard CMP, after which many material combinations can be bonded directly. Materials that do not polish readily may be bonded after the polishing of a very thin (<500 nm) bonding layer deposited on the native material. That layer can be any of several common (semi) insulating materials, including but not limited to SiO₂, SiN and AlO. "There are certainly things we can't bond to. We don't bond to metal," Milner said. "We're bonding silicon and glass and things of that ilk . . . semiconductor materials and their related oxides." Suitable materials include AlN, BeO, diamond, GaAs, GaN, glass, InP, LiN, quartz (fused and single-crystal), sapphire, fused silica, silicon, SiC and SiGe.

Various proprietary chemical activation treatments are possible, including dry-only or a combination of wet and dry process steps. The surface activation process facilitates spontaneous covalent bonds to form instantly when the prepared surfaces are brought together. Once activated, Ziptronix wafers have an activation shelf life of several hours, thereby facilitating high-volume, batch-driven production.

"One of the things that's different is that it's a room-temperature covalent bond, which means we are activating the atoms at the surface of each piece of material to look for and form spontaneously covalent or valent-sharing bonds with adjacent materials," Milner said. "The magic in the process is that we put the atoms at the surface of the material in that state, and they stay in that state for several hours until they find something to join with. That's the first piece of the magic that nobody else has been able to achieve. The second thing is that it's a covalent bond, which means that we're forming essentially — from a process viewpoint — a bulk material. Where the characteristics of the bond interface are completely uniform across the wafer, which means you can use conventional processing steps to cut vias through it and interconnect the devices from the top layer to the bottom layer."

Asked about common material bonding problems such as dislocations, Milner points to the work done at RTI. "We don't have to prove that the technology works; we have to implement it," he said. "It's manufacturable with a very high degree of confidence."

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